Patents by Inventor Simon Yi-Hung CHEN

Simon Yi-Hung CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of performing circuit simulation and generating circuit layout
    Patent number: 9411926
    Abstract: A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, the portion including a first device. A third netlist is generated based on the first netlist and the layout geometry parameters. A description in the third netlist for modeling the first device is decomposed into a description in a fourth netlist for modeling a plurality of secondary devices. The second netlist is generated based on the fourth netlist.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Simon Yi-Hung Chen
  • METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT
    Publication number: 20140282310
    Abstract: A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, the portion including a first device. A third netlist is generated based on the first netlist and the layout geometry parameters. A description in the third netlist for modeling the first device is decomposed into a description in a fourth netlist for modeling a plurality of secondary devices. The second netlist is generated based on the fourth netlist.
    Type: Application
    Filed: May 30, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Simon Yi-Hung CHEN
  • Method of performing circuit simulation and generating circuit layout
    Patent number: 8769476
    Abstract: A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Simon Yi-Hung Chen
  • METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT
    Publication number: 20130298091
    Abstract: A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Simon Yi-Hung CHEN