Patents by Inventor Simone Lavanga
Simone Lavanga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230253486Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.Type: ApplicationFiled: February 9, 2022Publication date: August 10, 2023Inventors: Simone Lavanga, Nicholas Dellas, Gerhard Prechtl, Luca Sayadi
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Patent number: 10403496Abstract: A method of forming a compound semiconductor substrate includes providing a crystalline base substrate having a first semiconductor material and a main surface, and forming a first semiconductor layer on the main surface and having a pair of tracks disposed on either side of active device regions. The first semiconductor layer is formed from a second semiconductor material having a different coefficient of thermal expansion than the first semiconductor material. The pair of tracks have a relatively weaker crystalline structure than the active device regions. The method further includes thermally cycling the base substrate and the first semiconductor layer such that the first semiconductor layer expands and contracts at a different rate than the base substrate. The pair of tracks physically decouple adjacent ones of the active device regions during the thermal cycling.Type: GrantFiled: August 30, 2017Date of Patent: September 3, 2019Assignee: Infineon Technologies Austria AGInventors: Simone Lavanga, Uttiya Chowdhury
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Patent number: 10403724Abstract: In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.Type: GrantFiled: September 4, 2018Date of Patent: September 3, 2019Assignee: Infineon Technologies AGInventors: Albert Birner, Helmut Brech, Simone Lavanga
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Patent number: 10204995Abstract: A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A layer of doped semiconductor material that fills the gate trench is formed. The doped semiconductor material in the gate trench locally depletes a subjacent section of the two-dimensional charge carrier gas channel at zero bias. A layer of electrically conductive material is formed on the doped semiconductor material. The layer of doped semiconductor material is structured to form a gate structure that includes a narrower portion of the doped semiconductor material that is disposed in the gate trench, a wider portion of the doped semiconductor material that is above the trench, and a gate electrode portion of the electrically conductive material that completely covers the wider portion of the doped semiconductor material.Type: GrantFiled: November 28, 2016Date of Patent: February 12, 2019Assignee: Infineon Technologies Austria AGInventors: Simone Lavanga, Marco Silvestri, Gilberto Curatola
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Publication number: 20180374921Abstract: In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.Type: ApplicationFiled: September 4, 2018Publication date: December 27, 2018Inventors: Albert Birner, Helmut Brech, Simone Lavanga
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Patent number: 10074721Abstract: In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.Type: GrantFiled: September 22, 2016Date of Patent: September 11, 2018Assignee: Infineon Technologies AGInventors: Albert Birner, Helmut Brech, Simone Lavanga
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Publication number: 20180151681Abstract: A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A layer of doped semiconductor material that fills the gate trench is formed. The doped semiconductor material in the gate trench locally depletes a subjacent section of the two-dimensional charge carrier gas channel at zero bias. A layer of electrically conductive material is formed on the doped semiconductor material. The layer of doped semiconductor material is structured to form a gate structure that includes a narrower portion of the doped semiconductor material that is disposed in the gate trench, a wider portion of the doped semiconductor material that is above the trench, and a gate electrode portion of the electrically conductive material that completely covers the wider portion of the doped semiconductor material.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Simone Lavanga, Marco Silvestri, Gilberto Curatola
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Publication number: 20180083107Abstract: In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.Type: ApplicationFiled: September 22, 2016Publication date: March 22, 2018Inventors: Albert Birner, Helmut Brech, Simone Lavanga
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Patent number: 9922936Abstract: A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V semiconductor substrate comprises one or more alignment features extending away from a main lateral surface. Each of the alignment features includes a first lateral surface that is vertically offset from the main lateral surface, and first and second vertical sidewalls that extend between the first lateral surface and the main lateral surface. An epitaxy blocker is formed on the first and second vertical sidewalls of each alignment feature. A type III-V semiconductor regrown layer is epitaxially grown on a portion of the semiconductor wafer that includes the one or more alignment features. The epitaxy blocker prevents the type III-V semiconductor regrown layer from forming on the first and second vertical sidewalls of the one or more alignment features.Type: GrantFiled: August 30, 2016Date of Patent: March 20, 2018Assignee: Infineon Technologies Austria AGInventors: Simone Lavanga, Uttiya Chowdhury, Mattia Capriotti
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Publication number: 20180061772Abstract: A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V semiconductor substrate comprises one or more alignment features extending away from a main lateral surface. Each of the alignment features includes a first lateral surface that is vertically offset from the main lateral surface, and first and second vertical sidewalls that extend between the first lateral surface and the main lateral surface. An epitaxy blocker is formed on the first and second vertical sidewalls of each alignment feature. A type III-V semiconductor regrown layer is epitaxially grown on a portion of the semiconductor wafer that includes the one or more alignment features. The epitaxy blocker prevents the type III-V semiconductor regrown layer from forming on the first and second vertical sidewalls of the one or more alignment features.Type: ApplicationFiled: August 30, 2016Publication date: March 1, 2018Inventors: Simone Lavanga, Uttiya Chowdhury, Mattia Capriotti
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Publication number: 20170365464Abstract: A method of forming a compound semiconductor substrate includes providing a crystalline base substrate having a first semiconductor material and a main surface, and forming a first semiconductor layer on the main surface and having a pair of tracks disposed on either side of active device regions. The first semiconductor layer is formed from a second semiconductor material having a different coefficient of thermal expansion than the first semiconductor material. The pair of tracks have a relatively weaker crystalline structure than the active device regions. The method further includes thermally cycling the base substrate and the first semiconductor layer such that the first semiconductor layer expands and contracts at a different rate than the base substrate. The pair of tracks physically decouple adjacent ones of the active device regions during the thermal cycling.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Inventors: Simone Lavanga, Uttiya Chowdhury
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Patent number: 9825139Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: GrantFiled: January 10, 2017Date of Patent: November 21, 2017Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Publication number: 20170287709Abstract: A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.Type: ApplicationFiled: April 5, 2016Publication date: October 5, 2017Inventors: Simone Lavanga, Uttiya Chowdhury
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Patent number: 9779935Abstract: A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.Type: GrantFiled: April 5, 2016Date of Patent: October 3, 2017Assignee: Infineon Technologies Austria AGInventors: Simone Lavanga, Uttiya Chowdhury
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Publication number: 20170148883Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: ApplicationFiled: January 10, 2017Publication date: May 25, 2017Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Patent number: 9564524Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: GrantFiled: May 28, 2015Date of Patent: February 7, 2017Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Publication number: 20150349105Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.Type: ApplicationFiled: May 28, 2015Publication date: December 3, 2015Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
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Patent number: 8952421Abstract: A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.Type: GrantFiled: October 15, 2012Date of Patent: February 10, 2015Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
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Patent number: 8900985Abstract: A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers.Type: GrantFiled: October 15, 2012Date of Patent: December 2, 2014Assignee: Infineon Technologies Austria AGInventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
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Publication number: 20140103398Abstract: A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga