Patents by Inventor Sin Sim Tan

Sin Sim Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to resolve instruction starvation
    Patent number: 7065596
    Abstract: Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: S. Steven Kulick, Rajee S. Ram, Sin Sim Tan, Rami A. Naqib
  • Method and apparatus for preventing starvation in a multi-node architecture
    Patent number: 6826619
    Abstract: A method of sending messages from a node to a receiving agent. In one embodiment, if a outbound message that is stored in a buffer in the node is unsuccessfully sent to the receiving agent more than a threshold number of times, outbound messages currently stored in the buffer are sent to the receiving agent. It is determined that these outbound messages have been successfully sent before any other outbound messages are sent to the receiving agent. In a further embodiment, an outbound message is successfully sent if a success confirmation message is received for the outbound message from the receiving agent. In a still further embodiment, a retry response is received from the receiving agent for an outbound message if a buffer in the receiving agent that stores incoming outbound messages does not have room for the outbound message.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: November 30, 2004
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Akhilesh Kumar, Sin Sim Tan
  • Method and apparatus to resolve instruction starvation
    Publication number: 20040068597
    Abstract: Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.
    Type: Application
    Filed: September 19, 2002
    Publication date: April 8, 2004
    Inventors: S. Steven Kulick, Rajee S. Ram, Sin Sim Tan, Rami A. Naqib
  • Coherent variable length reads from system memory
    Patent number: 6298420
    Abstract: Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: October 2, 2001
    Assignee: Intel Corporation
    Inventors: Suresh Chittor, Chih-Cheh Chen, Sin Sim Tan, Jonathan Nick Spitz
  • Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions
    Patent number: 6061764
    Abstract: Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: May 9, 2000
    Assignee: Intel Corporation
    Inventors: Suresh Chittor, Chih-Cheh Chen, Sin Sim Tan, Jonathan Nick Spitz