Abstract: Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

Abstract: Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

Abstract: A capability may include a pair of functions, one of which is integrated into a platform and the other of which is only available through an add-in card. A mating manager may determine whether both functions are available and if so, coordinate the operations of those functions. As a result, platforms may be released with the capability to be augmented thereafter by those users who choose to provide the add-in cards needed to implement the capability. A wireless network capability may be partially integrated into platforms, with additional components needed to actually implement the wireless capability provided through add-in cards. The add-in card may perform wake packet filtering to avoid excessively awakening the platform.

Abstract: A method and an apparatus for power management in a computer system have been disclosed. One embodiment of the method includes monitoring transactions over an interconnect coupling a chipset device and a peripheral device in the system, the transactions being transmitted between the peripheral device and the chipset device according to a flow control protocol to allow the chipset device to keep track of the transactions, and causing a processor in the system to exit from a power state if a plurality of coherent transactions pending in a buffer of the chipset device exceeds a first threshold. Other embodiments are described and claimed.

Abstract: A method to manage the power consumption of a display unit is provided. The method determines if a graphics-intensive event is occurring, uses a first refresh rate if the graphics-intensive event is occurring, and uses a second refresh rate different than the first refresh rate if the graphics-intensive event is not occurring. An apparatus for performing the method, and an article including a machine-accessible medium that provides instructions that, if executed by a processor, will cause the processor to perform the method are also provided.

Abstract: Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

Abstract: A method and an apparatus for power management in a computer system have been disclosed. One embodiment of the method includes monitoring transactions over an interconnect coupling a chipset device and a peripheral device in the system, the transactions being transmitted between the peripheral device and the chipset device according to a flow control protocol to allow the chipset device to keep track of the transactions, and causing a processor in the system to exit from a power state if a plurality of coherent transactions pending in a buffer of the chipset device exceeds a first threshold. Other embodiments are described and claimed.

Abstract: A method and apparatus for access to resources not mapped to an autonomous subsystem in a computer based system without involvement of the main operating system are described.

Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

Abstract: A method to manage the power consumption of a display unit is provided. The method determines if a graphics-intensive event is occurring, uses a first refresh rate if the graphics-intensive event is occurring, and uses a second refresh rate different than the first refresh rate if the graphics-intensive event is not occurring. An apparatus for performing the method, and an article including a machine-accessible medium that provides instructions that, if executed by a processor, will cause the processor to perform the method are also provided.

Abstract: A method and apparatus for serial communication with a co-processor. In one embodiment, a microprocessor is provided with a CPU core, set of serial interface registers, a serial interface unit, to provide serial communication between a co-processor and the microprocessor. The set of serial interface registers is part of a register file of the CPU core and interrupts are exchanged between the CPU core and the co-processor to allow for reading and writing of data placed in the serial registers of the register file.

Abstract: The present invention relates to an error correction and selective inversion circuit (ESIC). The ESIC includes a power-on logic state (POLS) bus having a data signal and an error code correction (ECC) generator having an input coupled to the POLS bus. The ECC generator includes one or more correction pins. The ESIC also includes an inversion generator having an input attached to the POLS bus in parallel with the ECC generator. The output of the inversion generator is integrated with the output of on or more correction pins from the ECC generator so as to form an inverted data signal output. An inverted data signal is recovered by the ESIC in an inversion recovery.

Abstract: A mechanism for conserving power consumption includes a processor, a memory, and a memory control hub (“MCH”). The memory is coupled to the processor and MCH is also coupled to the processor. MCH is further configured to switch between at least two power consumption modes for conserving power consumption.

Abstract: A capability may include a pair of functions, one of which is integrated into a platform and the other of which is only available through an add-in card. A mating manager may determine whether both functions are available and if so, coordinate the operations of those functions. As a result, platforms may be released with the capability to be augmented thereafter by those users who choose to provide the add-in cards needed to implement the capability. A wireless network capability may be partially integrated into platforms, with additional components needed to actually implement the wireless capability provided through add-in cards. The add-in card may perform wake packet filtering to avoid excessively awakening the platform.

Abstract: A mechanism for conserving power consumption includes a processor, a memory, and a memory control hub (“MCH”). The memory is coupled to the processor and MCH is also coupled to the processor. MCH is further configured to switch between at least two power consumption modes for conversing power consumption.

Abstract: The present invention relates to an error correction and selective inversion circuit (ESIC). The ESIC includes a power-on logic state (POLS) bus having a data signal and an error code correction (ECC) generator having an input coupled to the POLS bus. The ECC generator includes one or more correction pins. The ESIC also includes an inversion generator having an input attached to the POLS bus in parallel with the ECC generator. The output of the inversion generator is integrated with the output of on or more correction pins from the ECC generator so as to form an inverted data signal output. An inverted data signal is recovered by the ESIC in an inversion recovery.

Abstract: The present invention relates to an error correction and selective inversion circuit (ESIC). The ESIC includes a power-on logic state (POLS) bus having a data signal and an error code correction (ECC) generator having an input coupled to the POLS bus. The ECC generator includes one or more correction pins. The ESIC also includes an inversion generator having an input attached to the POLS bus in parallel with the ECC generator. The output of the inversion generator is integrated with the output of on or more correction pins from the ECC generator so as to form an inverted data signal output. An inverted data signal is recovered by the ESIC in an inversion recovery.

Abstract: A method for displaying graphics in a computer system. In one embodiment, the method includes a step of receiving a stream of data into the main memory of the computer system. This stream of data comprises a series of descriptions of digital video frames and a series of indicators, each of which corresponds to a set, or a group of one or more, of the video frame descriptions. Each indicator indicates a basis for selecting a subset of the set of video frame descriptions. For example, in one embodiment thirty video frame descriptions are in each set, and a given indicator indicates that half of those thirty descriptions should be included in the corresponding subset. Then, only the fifteen video frame descriptions selected for inclusion in the subset are decompressed, and only the fifteen resulting video frames are displayed, while the other fifteen frames are dropped.

Abstract: A method and apparatus for facilitating direct access to computer resources by a peripheral device while the computer's CPU is in a sleeping state. Said method and apparatus comprising a configurable link to enable a peripheral device to become the default system bus master when the main CPU is in a sleep state.