Patents by Inventor Sirui Luo

Sirui Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942473
    Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 26, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Sirui Luo, Srivatsan Parthasarathy, Piotr Olejarz, Daniel Boyko, Ara Arakelian, Stuart Patterson
  • Publication number: 20230402448
    Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Inventors: Sirui Luo, Srivatsan Parthasarathy, Piotr Olejarz, Daniel Boyko, Ara Arakelian, Stuart Patterson
  • Patent number: 10581423
    Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 3, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Srivatsan Parthasarathy, Sirui Luo, Thomas Paul Kearney, Yuanzhong Zhou, Donal Bourke, Jean-Jacques Hajjar
  • Publication number: 20200059228
    Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
    Type: Application
    Filed: January 2, 2019
    Publication date: February 20, 2020
    Inventors: Srivatsan Parthasarathy, Sirui Luo, Thomas Paul Kearney, Yuanzhong Zhou, Donal Bourke, Jean-Jacques Hajjar
  • Patent number: 10319714
    Abstract: High voltage drain-extended metal-oxide-semiconductor (DEMOS) bipolar switches for electrical overstress protection are provided. In certain configurations herein, an electrical overstress switch embodiment for providing electrical overstress protection, such as electrostatic discharge/electrical overstress (ESD/EOS) protection includes both a DEMOS device and an embedded bipolar device. The switch is implemented to achieve the advantages provided by the combined conduction of DEMOS and bipolar devices. For example, the DEMOS device provides surface conduction at the gate region for relatively fast switch device turn on and low voltage overshoot, while the bipolar device provides high current conduction during stress condition and a high holding voltage characteristics to prevent latch-up in mission critical integrated circuit applications.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 11, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Sirui Luo, Javier Alejandro Salcedo
  • Publication number: 20180211951
    Abstract: High voltage drain-extended metal-oxide-semiconductor (DEMOS) bipolar switches for electrical overstress protection are provided. In certain configurations herein, an electrical overstress switch embodiment for providing electrical overstress protection, such as electrostatic discharge/electrical overstress (ESD/EOS) protection includes both a DEMOS device and an embedded bipolar device. The switch is implemented to achieve the advantages provided by the combined conduction of DEMOS and bipolar devices. For example, the DEMOS device provides surface conduction at the gate region for relatively fast switch device turn on and low voltage overshoot, while the bipolar device provides high current conduction during stress condition and a high holding voltage characteristics to prevent latch-up in mission critical integrated circuit applications.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 26, 2018
    Inventors: Sirui Luo, Javier Alejandro Salcedo