Patents by Inventor Siu Chan
Siu Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080117701Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.Type: ApplicationFiled: January 25, 2008Publication date: May 22, 2008Inventors: Siu Chan, Raul-Adrian Cernea
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Publication number: 20080094911Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Inventor: Siu Chan
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Publication number: 20080087449Abstract: A rotary tool is provided with a head section that is selectively pivotable at a plurality of positions between an orientation where the head section is in-line with a body section to an orientation where the head section is perpendicular to the body section. The rotary tool can also swivel about an arc of 360 degrees.Type: ApplicationFiled: December 10, 2007Publication date: April 17, 2008Inventors: Chin Lam, Siu Chan
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Publication number: 20070263450Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.Type: ApplicationFiled: July 23, 2007Publication date: November 15, 2007Inventors: Raul-Adrian Cernea, Yan Li, Shahzad Khalid, Siu Chan
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Publication number: 20070230250Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.Type: ApplicationFiled: May 24, 2007Publication date: October 4, 2007Inventor: Siu Chan
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Publication number: 20070171725Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.Type: ApplicationFiled: December 29, 2005Publication date: July 26, 2007Inventor: Siu Chan
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Publication number: 20070115721Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: ApplicationFiled: January 18, 2007Publication date: May 24, 2007Inventors: Raul-Adrian Cernea, Siu Chan
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Publication number: 20070115722Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: ApplicationFiled: January 18, 2007Publication date: May 24, 2007Inventors: Raul-Adrian Cernea, Siu Chan
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Publication number: 20070084616Abstract: A rotary tool is provided with a head section that is selectively pivotable at a plurality of positions between an orientation where the head section is in-line with a body section to an orientation where the head section is perpendicular to the body section. The rotary tool can also swivel about an arc of 360 degrees.Type: ApplicationFiled: October 14, 2005Publication date: April 19, 2007Inventors: Chin Lam, Siu Chan
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Publication number: 20070086247Abstract: The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.Type: ApplicationFiled: October 14, 2005Publication date: April 19, 2007Inventors: Jeffrey Lutze, Yan Li, Siu Chan
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Publication number: 20070086251Abstract: The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.Type: ApplicationFiled: October 14, 2005Publication date: April 19, 2007Inventors: Jeffrey Lutze, Yan Li, Siu Chan
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Publication number: 20070014156Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.Type: ApplicationFiled: September 22, 2006Publication date: January 18, 2007Inventors: Yan Li, Seungpil Lee, Siu Chan
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Publication number: 20070014161Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.Type: ApplicationFiled: September 22, 2006Publication date: January 18, 2007Inventors: Yan Li, Seungpil Lee, Siu Chan
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Publication number: 20060221693Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Inventors: Raul-Adrian Cernea, Siu Chan
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Publication number: 20060221694Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Inventors: Raul-Adrian Cernea, Siu Chan
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Publication number: 20060209592Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.Type: ApplicationFiled: March 16, 2005Publication date: September 21, 2006Inventors: Yan Li, Seungpil Lee, Siu Chan
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Publication number: 20060158935Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.Type: ApplicationFiled: December 28, 2005Publication date: July 20, 2006Inventors: Siu Chan, Raul-Adrian Cernea
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Publication number: 20060158947Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.Type: ApplicationFiled: December 28, 2005Publication date: July 20, 2006Inventors: Siu Chan, Raul-Adrian Cernea
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Publication number: 20060140007Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.Type: ApplicationFiled: December 29, 2004Publication date: June 29, 2006Inventors: Raul-Adrian Cernea, Yan Li, Shahzad Khalid, Siu Chan
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Patent number: D413781Type: GrantFiled: October 23, 1998Date of Patent: September 14, 1999Assignee: Ching Wah Metal Ware Factory LimitedInventor: Siu Chan Wong