Abstract: A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.

Abstract: Disclosed is a computer having a display controller for controlling a display where the display provides an image with different selectable gray scale levels. The display controller includes a pattern unit for providing modulation patterns. The modulation patterns include patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related. The display controller additionally includes a modulation unit, operable over the sequential frames, for modulating the data values of pixels with the patterns whereby the intensity level of the pixels over the sequential frames is controlled as a function of the data value of the pixels and as a function of the patterns.

Abstract: An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

Abstract: A memory system is described which employs a plurality of "mostly good" memory chips. A redundant memory chip is used to store data designated to the defective locations in the mostly good memories. In one embodiment a PROM is programmed to recognize the addresses of the defective elements and to cause the redundant memory to be selected. In another embodiment, a content-addressable memory is employed to provide a new address in response to the addresses of defective elements in the mostly good memories.

Abstract: An MOS dynamic random-access memory (RAM) realizable as a 64K RAM is disclosed. Single transistor cells employing capacitive storage are coupled to folded bit-line halves. These bit-line halves are connected to sense amplifiers employing cross-coupled transistors. Boosting means employing a variable capacitance are coupled to the bit-line halves to boost the potential on a line during reading. The capacitor associated with each of the memory cells is coupled to a potential which is greater than the power supply potential. This plate potential is substantially constant and independent of power supply variations and is internally generated. The dummy cells employed within the RAM are charged in a unique manner to a substantially constant potential which does not vary with power supply variations.