Patents by Inventor Siva Kanakasabapathy
Siva Kanakasabapathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220005698Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Inventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
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Patent number: 11133189Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.Type: GrantFiled: March 1, 2019Date of Patent: September 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
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Patent number: 11054250Abstract: An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.Type: GrantFiled: April 11, 2018Date of Patent: July 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gangadhara Raja Muthinti, Chiew-Seng Koay, Siva Kanakasabapathy, Nelson Felix
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Patent number: 11024715Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.Type: GrantFiled: February 21, 2020Date of Patent: June 1, 2021Assignee: Tessera, Inc.Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
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Patent number: 10741660Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.Type: GrantFiled: June 12, 2018Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicolas J. Loubet, Siva Kanakasabapathy, Kangguo Cheng, Jingyun Zhang
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Patent number: 10734234Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.Type: GrantFiled: December 18, 2017Date of Patent: August 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
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Publication number: 20200243648Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.Type: ApplicationFiled: February 21, 2020Publication date: July 30, 2020Applicant: TESSERA, INC.Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
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Patent number: 10692990Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.Type: GrantFiled: October 11, 2019Date of Patent: June 23, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
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Patent number: 10644129Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.Type: GrantFiled: October 11, 2019Date of Patent: May 5, 2020Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
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Patent number: 10622482Abstract: Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.Type: GrantFiled: May 3, 2019Date of Patent: April 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew M. Greene, Ekmini Anuja De Silva, Siva Kanakasabapathy
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Patent number: 10600868Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.Type: GrantFiled: January 10, 2019Date of Patent: March 24, 2020Assignee: Tessera, Inc.Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
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Publication number: 20200044051Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
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Publication number: 20200044052Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
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Patent number: 10553700Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.Type: GrantFiled: May 29, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
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Publication number: 20190378906Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Inventors: Nicolas J. Loubet, Siva Kanakasabapathy, Kangguo Cheng, Jingyun Zhang
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Patent number: 10504798Abstract: Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.Type: GrantFiled: February 15, 2018Date of Patent: December 10, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Chanro Park, Laertis Economikos, Andrew Greene, Siva Kanakasabapathy, John R. Sporre
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Publication number: 20190371912Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
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Publication number: 20190316900Abstract: An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.Type: ApplicationFiled: April 11, 2018Publication date: October 17, 2019Inventors: Gangadhara Raja Muthinti, Chiew-seng Koay, Siva Kanakasabapathy, Nelson Felix
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Publication number: 20190259665Abstract: Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.Type: ApplicationFiled: May 3, 2019Publication date: August 22, 2019Inventors: Andrew M. Greene, Ekmini Anuja De Silva, Siva Kanakasabapathy
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Publication number: 20190252268Abstract: Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.Type: ApplicationFiled: February 15, 2018Publication date: August 15, 2019Inventors: Ruilong Xie, Chanro Park, Laertis Economikos, Andrew M. Greene, Siva Kanakasabapathy, John R. Sporre