Abstract: A memory system having a memory controller plus one or more registered memory modules, each registered memory module having a bank of memory chips and an associated register. A pre-register address/command bus connects the memory controller with the associated register. Each registered memory module has a post-register command/address bus that connects the memory chips in parallel with the associated register. The post-register command/address bus terminates with termination resistors that are connected to a voltage level that is approximately half of the supply voltage level. The memory controller provides chip select signals to the associated register of the registered memory modules. The associated registers, however, switch command/address signals to the memory chips independent of the chip select signals.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for generating the output signal and a second circuit having first and second terminals. The first terminal is coupled to the first circuit and the second terminal is coupled to the interface port. A signal level at the first terminal corresponds to a first combination of the input and output signals, and a signal level at the second terminal corresponds to a second combination of the input and output signals. A third circuit is coupled to the first and second terminals of the second circuit for determining the input signal based on the first and second combinations of the input and output signal levels.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for generating the output signal and a second circuit having first and second terminals. The first terminal is coupled to the first circuit and the second terminal is coupled to the interface port. A signal level at the first terminal corresponds to a first combination of the input and output signals, and a signal level at the second terminal corresponds to a second combination of the input and output signals. A third circuit is coupled to the first and second terminals of the second circuit for determining the input signal based on the first and second combinations of the input and output signal levels.