Patents by Inventor Sivakumar Arulanantham

Sivakumar Arulanantham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock re-convergence pessimism removal through pin sharing during clock tree planning
    Patent number: 11914939
    Abstract: A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 27, 2024
    Assignee: Synopsys, Inc.
    Inventors: Prashant Gupta, Shibaji Banerjee, Sivakumar Arulanantham
  • Automated balanced global clock tree synthesis in multi level physical hierarchy
    Patent number: 11704467
    Abstract: Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: July 18, 2023
    Assignee: Synopsys, Inc.
    Inventors: Ashima Sahil Dabare, Sanjiv Mathur, Anusha Reddy Sindhwala, Prakasha Karkada Holla, Sivakumar Arulanantham, Srinivasan Krishnamurthy, Chun-Cheng Chi, Shih-Pin Hung
  • AUTOMATED BALANCED GLOBAL CLOCK TREE SYNTHESIS IN MULTI LEVEL PHYSICAL HIERARCHY
    Publication number: 20210390242
    Abstract: Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 16, 2021
    Inventors: Ashima Sahil Dabare, Sanjiv Mathur, Anusha Reddy Sindhwala, Prakasha Karkada Holla, Sivakumar Arulanantham, Srinivasan Krishnamurthy, Chun-Cheng Chi, Spin Hung