Patents by Inventor Sivakumar Mudanai

Sivakumar Mudanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150021553
    Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Applicant: INTEL CORPORATION
    Inventors: ANNALISA CAPPELLANI, KELIN J. KUHN, RAFAEL RIOS, Titash Rakshit, Sivakumar Mudanai
  • Patent number: 8853741
    Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Titash Rakshit, Sivakumar Mudanai
  • Publication number: 20130334572
    Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 19, 2013
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Titash Rakshit, Sivakumar Mudanai
  • Patent number: 7650271
    Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Frank P. O'Mahony, Haydar Kutuk, Bryan K. Casper, Eyal Fayneh, Sivakumar Mudanai, Wei-kai Shih, Farag Fattouh
  • Publication number: 20070233444
    Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Frank O'Mahony, Haydar Kutuk, Bryan Casper, Eyal Fayneh, Sivakumar Mudanai, Wei-kai Shih, Farag Fattouh
  • Publication number: 20070145495
    Abstract: A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 28, 2007
    Inventors: Giuseppe Curello, Sivakumar Mudanai, Nick Lindert, Leonard Pipes, M. Shaheed, Sunit Tyagi