Abstract: The present disclosure provides systems, devices, and methods for data storage. Systems and devices for data storage may include memory cells with a first electrode, a second electrode, and a switching medium electrically coupled to the first and second electrode. The switching medium may be configured to provide or may provide a conductive path. The switching medium may be configured to provide or may provide a plurality of resistance states. A resistance state of the switching medium may be changed by application of different voltage biases for a period of time, a constant voltage for different periods of time, or a voltage of a different polarity as comparted to a previously applied voltage. Data may be written to a memory cell by changing the resistance state of the switching medium. Data may be accessed by sensing or detecting the resistance of the switching medium.

Abstract: To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as branch prediction, register usage, overflow, a history of branch predictions of groups of branches combined, and a history of register usage for: dynamically modifying instruction parameters of an emulation sequence of instructions; reordering emulated instructions; and adding or changing the dynamic execution information.

Abstract: The performance of a system is simulated in a method comprising: performing simulation in a first simulation mode for at least a first portion of code that models at least a portion of the system; and performing simulation in a second simulation mode for at least a second portion of code that models at least a portion of the system.

Abstract: A data processor includes at least one instruction pipeline for executing an instruction stream having branch instructions. The choices of a branch instruction, the next inline instruction or a target instruction, are made available for selection by a control bypass signal that is generated during decode of the branch instruction.

Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible with a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. Switching between 16-bit instruction execution and 32-bit instruction execution is accomplished by branch instructions that employ a least significant bit position of the address of the target of the branch to identify whether the target instruction is a 16-bit instruction or a 32-bit instruction.

Abstract: An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or mote associated branch instructions. Because branch target address computation information is disassociated from the actual branch instruction, more space is available within the branch instruction itself to permit additional new types of operations, such as folded-compare, register to register comparisons (including a compare to a zero valued register), predicate evaluations, etc.

Abstract: A data processor includes at least one instruction pipeline for executing an instruction stream having branch instructions. The choices of a branch instruction, the next inline instruction or a target instruction, are made available for selection by a control bypass signal that is generated during decode of the branch instruction.

Abstract: A thermoplastic molding composition comprising a transparent resinous component suitable for tinting by dip-dye method is disclosed. The resinous component is selected from the group consisting of (i) a blend of (co)polycarbonate resin and (co) polycaprolacone, and (ii) a copolymer containing carbonate and caprolactone structural units. The composition, characterized in that it is free of photochromic colorants, may be molded by thermoplastic means, and the molded article is then dipped-dyed by immersion in a tinting solution. The tinted articles are suitable for making, among others, optical lenses.

Abstract: In a repeated sequence of instructions of a procedure based language, multiple entry points and/or exit points, that is access points, control repetitions and create multiple code segments. At least one segment is executed fewer times than the number of repetitions n that the entire sequence of instructions is called. At least one of the repetitions has extra code that is not necessary in all or some of the repetitions, and the extra code is isolated by the added access points, to improve speed of execution through reduction of machine cycles. In contrast to the external call entry and exit points, for example, the added entry and/or exit point is used only within the function itself during repetitions. When executed, the internal calls of added entry and/or exit points cause one segment to have fewer repetitions than another segment. A specific example is that of a recursive sequence of instructions.

Abstract: To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as branch prediction, register usage, overflow, a history of branch predictions of groups of branches combined, and a history of register usage for: dynamically modifying instruction parameters of an emulation sequence of instructions; reordering emulated instructions; and adding or changing the dynamic execution information.

Abstract: A system and method for implementing a computing system and associated programs with optimized branch instruction execution is disclosed. Branch operations are divided into two parts, with a branch control (prepare to branch) preceeding a branch instruction in the instruction stream, so that a pipeline in the computing system can be set up in advance to load appropriate target instructions. In this manner, instruction flow can be easily re-directed if the branch instruction is accurately predicted. Predictions on the branch condition are used to speculatively prefetch and load instructions as needed. In most cases, branch execution penalties caused by target address calculation latencies, instruction cache latencies and/or mis-predictions, can be significantly reduced.

Abstract: The performance of a system is simulated in a method comprising: performing simulation in a first simulation mode for at least a first portion of code that models at least a portion of the system; and performing simulation in a second simulation mode for at least a second portion of code that models at least a portion of the system.

Abstract: An improved branch instruction and associated branch control instruction are provided for optimizing handling of branch operations within a pipelined processor. The branch control instruction is adapted so that it can precede the branch instruction in a program sequence and provides branch target address computation information so that branch target addresses can be computed in advance of execution of one or more associated branch instructions. The branch control instruction also includes its own branch instruction prediction bit for specifying to a prefetcher within the processor whether a common branch instruction is likely to be needed by the processor, as well as a ranking field for specifying a preloading priority for the particular common branch instruction.

Abstract: According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to the present invention can be operative on a variety of computer architectures, including RISC architectures.

Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.

Abstract: A processor and accompanying program are disclosed which utilize branch control instructions in cooperation with branch instructions to reduce branch latency. The branch control instruction and branch instruction have a format/structure that is designed to execute flexibly and efficiently by making use of separate dedicated target address and target branch instruction register sets used by a pipeline within the processor.

Abstract: A thermoplastic molding composition comprising a transparent resinous component suitable for tinting by dip-dye method is disclosed. The resinous component is selected from the group consisting of (i) a blend of (co)polycarbonate resin and (co)polycaprolacone, and (ii) a copolymer containing carbonate and caprolactone structural units. The composition, characterized in that it is free of photochromic colorants, may be molded by thermoplastic means, and the molded article is then dipped-dyed by immersion in a tinting solution. The tinted articles are suitable for making, among others, optical lenses.

Abstract: A process for making a photochromic optical lens is disclosed. In a first embodiment of the process a multi-plied laminate, containing a ply of photochromic thermoplastic polyurethane (herein “TPU”) and a ply containing thermoplastic polycarbonate, is first placed in the cavity of a suitable mold. The ply that contains polycarbonate resin is placed facing the cavity. Thermoplastic polycarbonate resin is then injected into the cavity. In a second embodiment, referred to as an over-mold method, polycarbonate is first injection molded into a molding cavity to form a substrate. Photochromic TPU is, in a subsequent step, injected into the cavity to form a superstrate overlay. In both embodiments, the articles thus molded are suitable for the preparation of optical lenses.

Abstract: A dual mode branch and branch control system and method is disclosed for accommodating a processor that can operate in either of two operating modes, each using a different type of branch instruction. In a first instruction set, a first type branch instruction includes a separate branch instruction and a branch control instruction, while in the second instruction set, a second type branch instruction includes only a branch instruction. The processor is optimized to handle the first instruction set so that the branch instruction is arrangeable in a program sequence so that an execution unit in the processor can compute a branch target address based on the branch control instruction without a latency penalty. The first type branch instructions also include a folded-compare format, while the second type branch instructions have separated compare and branch instructions.

Abstract: The present invention resides in the surprising properties found to characterize the thermoplastic molding composition which comprise a polydiorganosiloxane block copolycarbonate and an additive amount of a partially fluorinated polyolefin. The composition of the invention has a surprisingly improved flame retardance and a high impact strength.