Patents by Inventor Sivarama K. Kodukula

Sivarama K. Kodukula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7457893
    Abstract: A method is disclosed for dynamically selecting software buffers for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain of software buffers. Current characteristics of the system are determined. Software buffers to be combined are then dynamically selected. This selection is made according to the characteristics of the system in order to maximize performance of the system.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: James R. Gallagher, Ron Encarnacion Gonzalez, Binh K. Hua, Sivarama K. Kodukula
  • Publication number: 20080259917
    Abstract: A method for Ethernet packet load balancing includes receiving a transmit package for transmission on an Ethernet network. An offload adapter identifies a least busy port from a plurality of ports indicated in a port list, based on a byte count associated with each of the plurality of ports. The offload adapter determines whether the identified least busy port is in a working status. In the event the identified least busy port is in a working status, the offload adapter assigns the transmit packet to the identified least busy port and increments the byte count associated with the identified least busy port. In the event the identified least busy port is not in a working status, the offload adapter updates the port list and, based on a determination that there are additional working ports, assigns the transmit packet to one of the additional working ports.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Inventors: Binh K. Hua, Ron E. Gonzalez, Sivarama K. Kodukula, Rakesh Sharma
  • Publication number: 20080232349
    Abstract: Method, system and computer program product for transferring data in a data processing system network. A method for transferring data in a data processing system network according to the invention includes determining an adapter among a plurality of adapters that has the lowest transmit latency, and assigning data to be transferred to the adapter determined to have the lowest transmit latency. The data to be transferred is then transferred by the assigned adapter. The present invention utilizes network adapters to transfer data in a more efficient manner.
    Type: Application
    Filed: June 2, 2008
    Publication date: September 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James R. Gallagher, Binh K. Hua, Hong Lam Hua, Sivarama K. Kodukula
  • Publication number: 20080225733
    Abstract: Methods and arrangements to monitor communication components such as a network adapters for activity, and identify components that have lower than normal levels of activity are provided. An identified communication component can become suspect component and a candidate for further testing, including different forms of interrogation. Process for interrogating candidates can include generating and sending test packets having the media access control (MAC) address of the candidate to the candidate and if activity is not detected subsequent to the interrogation, the candidate can be flagged as a failed component. Correspondingly, the component can be deactivated and removed from service. In a further embodiment, a backup component can be activated and assume the role previously held by the failed component.
    Type: Application
    Filed: May 30, 2008
    Publication date: September 18, 2008
    Inventors: Binh K. Hua, Sivarama K. Kodukula
  • Publication number: 20080209087
    Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.
    Type: Application
    Filed: May 6, 2008
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herman Dietrich Dierks,, Binh K. Hua, Sivarama K. Kodukula
  • Patent number: 7403479
    Abstract: Method, system and computer program product for transferring data in a data processing system network. A method for transferring data in a data processing system network according to the invention includes determining an adapter among a plurality of adapters that has the lowest transmit latency, and assigning data to be transferred to the adapter determined to have the lowest transmit latency. The data to be transferred is then transferred by the assigned adapter. The present invention utilizes network adapters to transfer data in a more efficient manner.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: James R. Gallagher, Binh K. Hua, Hong Lam Hua, Sivarama K. Kodukula
  • Publication number: 20080133796
    Abstract: A method, system, and computer program product in a data processing system are disclosed for dynamically selecting software butters for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain of software buffers. Current characteristics of the system are determined. Software buffers to be combined are then dynamically selected. This selection is made according to the characteristics of the system in order to maximize performance of the system.
    Type: Application
    Filed: January 11, 2008
    Publication date: June 5, 2008
    Inventors: James R. Gallagher, Ron Encarnacion Gonzalez, Binh K. Hua, Sivarama K. Kodukula
  • Publication number: 20080133981
    Abstract: Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.
    Type: Application
    Filed: November 15, 2007
    Publication date: June 5, 2008
    Inventors: JAMES R. GALLAGHER, Binh K. Hua, Sivarama K. Kodukula, Bruce Henry Ratcliff
  • Patent number: 7376763
    Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventors: Herman Dietrich Dierks, Jr., Binh K. Hua, Sivarama K. Kodukula
  • Patent number: 7359315
    Abstract: A method, system, and computer program product are disclosed in a data processing system for avoiding data loss during network port recovery. A first network port is linked to a second network port via a network. The second network port transmits data to the first network port via the network. A determination is made that the first network port needs to be reinitialized. Prior to the first network port executing a re-initialization process, the first network port notifies the second network port to pause its data transmissions to the first network port.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: April 15, 2008
    Assignee: In-ernational Business Machines Corporation
    Inventors: Binh K. Hua, Hong Lam Hua, Sivarama K. Kodukula
  • Publication number: 20080084828
    Abstract: A method to dynamically adjust the number of active Ethernet adapters in a EtherChannel group, the method including: monitoring a total EtherChannel throughput; determining availability of unused Ethernet adapters if the throughput is above a first predetermined throughput; powering up and adding an unused Ethernet adapter to the EtherChannel group if the throughput is above the first predetermined throughput; powering down and removing an active Ethernet adapter from the EtherChannel group if the throughput is less than the second predetermined throughput; and continue monitoring the total EtherChannel throughput after sleeping for a selected period of time. Accordingly, when an adapter is removed from the EtherChannel group, power to the removed adapter is cut off to reduce power consumption and reduce generation of thermal heat, thus increasing a potential lifespan of the plurality of adapters.
    Type: Application
    Filed: October 9, 2006
    Publication date: April 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ron E. Gonzalez, Binh K. Hua, Sivarama K. Kodukula, Rakesh Sharma
  • Patent number: 7356664
    Abstract: A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the memory, wherein the frame is transferred from the memory to the network adapter.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Herman Dietrich Dierks, Jr., Binh K. Hua, Sivarama K. Kodukula
  • Patent number: 7310766
    Abstract: Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: December 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: James R. Gallagher, Binh K. Hua, Sivarama K. Kodukula, Bruce Henry Ratcliff
  • Publication number: 20040252638
    Abstract: A method in a data processing system for managing transmission of pause frames. In response to detecting an overflow condition during a receipt of data from a network, enabling flow control in response to detecting the overflow condition. The flow control is enabled as long as the overflow condition is present. A determination is made as to whether the operating system unavailable after a period of time passes. If the operating system believed to have crashed and flow control is enabled, the flow control is disabled.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Ron Encarnacion Gonzalez, Binh K. Hua, Sivarama K. Kodukula
  • Patent number: 5581741
    Abstract: A programmable I/O bus adapter for interfacing and controlling two data processing systems having dissimilar and incompatible architectures. The programmable I/O bus adapter is capable of controlling the I/O bus and adapters of each of the two data processing systems. Simultaneously, the I/O bus adapter provides for interfacing and communication between the two dissimilar data processing systems. Interfacing from the bus adapter to each data processing system is provided by circuitry provided on integrated circuit chip sets specifically designed to interface with each system. The interfacing circuitry is enabled to convert signals between each system to allow for communication. Communication paths couple the adapter to the I/O bus of each system. The ability to access and control an I/O bus and adapter of each system is provided by a microprocessor having microcode instructions stored in programmable memory.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: December 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Alan R. Clark, Sivarama K. Kodukula
  • Patent number: 5381480
    Abstract: A system translates a first group of cipher blocks based on a first encryption key to a second group of respective cipher blocks based on a second encryption key. Respective cipher blocks of the first and second groups represent the same data. The system comprises decryption hardware for sequentially decrypting the cipher blocks of the first group based on the first key. Encryption hardware is coupled to receive decrypted blocks output from the decryption hardware and sequentially encrypts the decrypted blocks into respective cipher blocks of the second group based on the second encryption key. A control unit controls the encryption hardware to encrypt the decrypted blocks into the respective cipher blocks of the second group while the decryption hardware decrypts cipher blocks of the first group. Consequently, decryption and encryption operations occur in parallel and the translation process is expedited.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: January 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Adrian S. Butter, Brian S. Finkel, Chang-Yung Kao, Sivarama K. Kodukula, James P. Kuruts
  • Patent number: 5317638
    Abstract: ANSI X3.92 Data Encryption algorithm is public knowledge, and is widely used where data security and integrity is vital, such as commercial banks, secret service organizations etc. Even though this algorithm is feasible to implement in software, it is impractical to achieve desired performance for most of the applications. Hence, a hardware solution is highly recommended. Prior art DES hardware in CMOS technology served performance needs of low-end and mid-range systems only, due to the technology constraints. However, some of these constraints are removed through the technology breakthroughs and the current CMOS is well suited for high performance applications. While prior art DES designs allowed one round per cycle to minimize the cell count, the current technology allows of multiple rounds per cycle due to the denser CMOS chip technology.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: Chang Y. Kao, James P. Kuruts, Sivarama K. Kodukula
  • Patent number: 4972317
    Abstract: A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.
    Type: Grant
    Filed: August 4, 1989
    Date of Patent: November 20, 1990
    Assignee: International Business Machines Corp.
    Inventors: Joseph P. Buonomo, Robert W. Callahan, Steven R. Houghtalen, Sivarama K. Kodukula, Raymond E. Losinger, Brion N. Shimamoto, Harry L. Tredennick, James W. Valashinas