Abstract: A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

Abstract: Methods, apparatuses, and systems are described related a data receiver circuit having a pair of offset edge samplers to sample a data signal, at an edge sampling time between data samples, with respect to different reference levels. A clock-data recovery (CDR) circuit of the receiver circuit may determine an A-count that corresponds to a number of times the signal level of the data signal at the edge sampling time is between the reference levels of the offset edge samples to provide a signal integrity metric for the receiver circuit. The CDR circuit may dynamically update its settings based on the A-count.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Methods, apparatuses, and systems are described related a data receiver circuit having a pair of offset edge samplers to sample a data signal, at an edge sampling time between data samples, with respect to different reference levels. A clock-data recovery (CDR) circuit of the receiver circuit may determine an A-count that corresponds to a number of times the signal level of the data signal at the edge sampling time is between the reference levels of the offset edge samples to provide a signal integrity metric for the receiver circuit. The CDR circuit may dynamically update its settings based on the A-count.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.