Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: An apparatus for creating or modifying browser-renderable teaching objects for use in creating a browser-renderable textbook data object. The apparatus includes a database, a network interface for receiving a source file containing codes for creating or modifying the browser-renderable teaching objects by way of a network, and a processor configured to create or modify the teaching objects based on the codes, and store the teaching objects in the database. A first code instructs the processor to create at least one browser-renderable section object for the textbook data object, the first code including a first attribute configured to instruct the processor to configure the at least one section object such that, when rendered by a browser module, a specified section title is provided at a beginning of the at least one section object; and (2) set of codes configured to instruct the processor to create or modify the teaching objects within the at least one section object.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: Methods and apparatuses for designing an integrated circuit (IC). In one exemplary method, a hardware description language (HDL) code is compiled to produce a representation of logic, and a portion of this representation of logic is allocated to a first physical portion of an area of the IC. This portion is reallocated automatically, according to machine determined parameters, such that a modified portion of the representation is allocated to the first physical portion. Examples of this reallocating include moving logic between regions on the IC, replicating logic based on the regions of the IC, decomposing RTL instances into elements based on information concerning the regions, reducing logic path crossings of a region's boundaries, and assuring that the original allocation or the result of a reallocation can be accommodated by the first physical portion of the IC.