Abstract: A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.

Abstract: For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform invariant node, and the second timing arc generation factors only the uniform waveform. Similarly, a setup arc employs the uniform waveform rather than multiple clock input waveforms in computing setup/hold values. Simulation of waveform propagation is also simplified by simulating only the uniform waveform for the second portion. Additionally, the first arc may be shared between a plurality of circuit paths which share an input pin and the waveform invariant node.

Abstract: Systems and methods for generating Extracted Timing Models (ETM) for use in an analysis of the timing of an integrated circuit design in which common paths that contribute to Common Path Pessimism (CPP) are identified and included in the generated ETM such that a CPP removal algorithm implemented during the timing analysis will be properly adjusted to remove such pessimism. To generate an ETM, the clock latency paths will be characterized, taking into account the pins and timing arcs that are necessary for the identification and removal of common path pessimism, the timing information of the topologically crucial points of the design block will be retained in the ETM, and the non-essential and noisy information will be removed from the ETM to ensure that the ETM is robust and compact.