Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.

Abstract: A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.

Abstract: A vertical memory device includes a substrate, first and second sub-semiconductor patterns, first and second common source contacts, and first and second cell structures. The substrate includes a first region and a second region having a same length as the first region in a first direction, the first region having a first width in a second direction perpendicular to the first direction, and the second region having a second width in the second direction that is less than the first width. The first sub-semiconductor pattern covers the first region, and a portion of the first sub-semiconductor pattern has a first thickness. The second sub-semiconductor pattern covers the second region and has a second thickness that is less than the first thickness. The first and second common source contacts are disposed on edges in the second direction of the first and second patterns, respectively.

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

Abstract: A motor assembly including: a housing that forms an accommodating space therein; a stator that is provided inside the housing; and a rotor that is rotatable with respect to the stator, wherein the housing includes: a cooling water passage through which cooling water exchanges heat while moving therein; and an air flow passage through which air inside the accommodation space exchanges heat while moving through the housing in the axial direction. Accordingly, the air inside the housing can be cooled to a preset temperature or less.

Abstract: Provided are various mechanisms and processes for generating dynamic merchant scoring predictions. A system is configured to receive datasets comprising pairings between training customer profiles and training merchant profiles. For each pairing, a set of feature values corresponding to features specified by the customer and merchant profiles are extracted and converted into a training vector to train a machine learning model to determine a weighted coefficient for each feature. Once sufficiently trained, the system determines a set of available merchant profiles for a customer profile in response to receiving a search request from a customer associated with the customer profile. For each pairing between the customer profile and an available merchant profile, the system determines an order score for the available merchant based on the weighted coefficients and an input set of feature values specified by the customer profile and the available merchant profile.

Abstract: A semiconductor device includes a substrate having a recess therein that is partially filled with at least two semiconductor active regions. The recess has sidewalls and a bottom that are sufficiently lined with corresponding substrate insulating layers that the at least two semiconductor active regions are electrically isolated from the substrate, which surrounds the sidewalls and bottom of the recess. A sidewall insulating layer is provided, which extends as a partition between first and second ones of the at least two semiconductor active regions, such that the first and second ones of the at least two semiconductor active regions are electrically isolated from each other. First and second gate electrodes are provided in the first and second active regions, respectively.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain. region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

Abstract: Provided are various mechanisms and processes for generating dynamic merchant scoring predictions. A system is configured to receive datasets comprising pairings between training customer profiles and training merchant profiles. For each pairing, a set of feature values corresponding to features specified by the customer and merchant profiles are extracted and converted into a training vector to train a machine learning model to determine a weighted coefficient for each feature. Once sufficiently trained, the system determines a set of available merchant profiles for a customer profile in response to receiving a search request from a customer associated with the customer profile. For each pairing between the customer profile and an available merchant profile, the system determines an order score for the available merchant based on the weighted coefficients and an input set of feature values specified by the customer profile and the available merchant profile.

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.