Patents by Inventor Socrates Vamvakos

Socrates Vamvakos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DIGITAL PHASE LOCKED LOOP WITH DITHERING
    Publication number: 20110148676
    Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 23, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Khurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski, Socrates Vamvakos
  • Digital phase locked loop with dithering
    Patent number: 7920081
    Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: April 5, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski, Socrates Vamvakos
  • DIGITAL PHASE LOCKED LOOP WITH DITHERING
    Publication number: 20100283654
    Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
    Type: Application
    Filed: July 22, 2010
    Publication date: November 11, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Khurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski, Socrates Vamvakos
  • Digital phase locked loop with dithering
    Patent number: 7786913
    Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski, Socrates Vamvakos
  • DIGITAL PHASE LOCKED LOOP WITH DITHERING
    Publication number: 20080315928
    Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 25, 2008
    Inventors: Khurram WAHEED, Mahbuba Sheba, Robert Bogdan Staszewski, Socrates Vamvakos