Abstract: A semiconductor power device and a method for manufacturing the same is provided. The semiconductor power device includes a semiconductor body including a conductive substrate and an epitaxial layer of a first charge type grown on the conductive substrate, and one or more inner wells of a second charge type different from the first charge type in an active area of the semiconductor power device. At least some of the one or more inner wells of the second charge type are formed using at least two ion implantation steps. One step is dedicated to forming the inner wells of the second type whereas one or more further ion implantation steps are simultaneously used for forming a respective JTE structure and for increasing a dopant concentration of at least one well of the second charge type.

Abstract: A semiconductor device is provided, including: a lead frame, a semiconductor chip, a mold, and an adhesion promoter. The lead frame includes a first surface and a second frame surface opposite the first surface, and the chip includes a first and a second surface opposite the first surface, the first frame surface is an outer surface of the device, with the second frame surface attached to the first chip surface so that the second frame surface is partially covered by the first chip surface. An uncovered surface part of the second frame surface and the second chip side are in contact with the mold by the adhesion promoter, that is on the uncovered surface part of the second frame surface and/or on the second chip surface. The adhesion promoter enhances adhesion between the mold, and either the second frame surface or the second chip surface of the chip.

Abstract: An MPS diode and a manufacturing method is provided. The diode includes a semiconductor body including an active area and an adjacent termination area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second type different from the first conductivity type, the wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the wells. The drift region includes a doped region surrounding each of the wells and having a higher dopant concentration than a remainder of the drift region, and the doped region is spaced apart from the termination area.

Abstract: Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.

Abstract: A vertical semiconductor component including: a substrate; an epitaxial layer doped with a first conductivity type, preferably n-doped, provided on the substrate; a metal layer deposited on the epitaxial layer to form a Schottky contact with the epitaxial layer; a plurality of first regions embedded in the epitaxial layer and contacting the metal layer, and doped with a second conductivity type, in order to form a plurality of pn-junctions with the epitaxial layer; and a plurality of second regions embedded in a first region and contacting the metal layer, and doped with a second conductivity type, at a higher concentration, in order to form a plurality of low-resistance ohmic contacts with the metal layer. The semiconductor component includes a lateral cross section along which there are more first regions than second regions.

Abstract: A semiconductor product, including: a base region doped with a first conductivity type; a plurality of stripe regions doped with a second conductivity type, provided on an upper surface of the base region, and the second conductivity type is different from the first conductivity type; a plurality of cell regions doped with the second conductivity type, provided on the upper surface of the base region; and a metal layer arranged on the upper surface of the base region, so that the metal layer defines a Schottky barrier with the base region and covers the plurality of stripe regions and the plurality of cell regions; and each cell region of a majority of the plurality of cell regions contacts at least one neighboring stripe region of the plurality of stripe regions and the stripe regions and the cell regions extend into the base region to different depths.

Abstract: A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.

Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.

Abstract: A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.

Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.

Abstract: A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has comprises a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.

Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.

Abstract: A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

Abstract: The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.

Abstract: A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.

Abstract: Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses.

Abstract: The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.

Abstract: Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses.

Abstract: The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.