Abstract: The present disclosure describes a device including an initiator, a target, a communication bus coupling the initiator to the target over a channel, a functional circuit, and an error logger circuit. The functional circuit is coupled to the channel and can perform a function associated with a transaction request from the initiator to the target. The functional circuit can include an error detection circuit to detect an error associated with the function performed by the functional circuit and to generate an error indicator signal to indicate that the error has been detected. The error logger circuit can be coupled to the functional circuit, in which the error logger circuit is configured to receive the error indicator signal from the error detection circuit and store information about the error.

Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.

Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.

Abstract: Embodiments related to arbitration are described and depicted.

Abstract: Router IP port for an IP router of a IP network system, wherein the router IP port comprises: an encapsulating unit for encapsulating IP data packets received from an IP sub-network to generate Ethernet data packets which are forwarded to an Ethernet unit of said IP router; a decapsulating unit for decapsulating Ethernet data packets received from said Ethernet unit to extract IP data packets to be forwarded; an Egress filter unit for filtering the decapsulated IP data packets extracted by said decapsulating unit in response to a match signal which is generated by an Egress comparison unit which compares a hierarchical destination address prefix of said decapsulated IP data packets logically with configuration data stored in a local memory of said router port.

Abstract: Embodiments related to arbitration are described and depicted.

Abstract: A data processing arrangement including a plurality of processing units. Each processing unit has a processing element, a data memory, a fill level unit, and a control unit. The processing element processes data stored in the data memory, or the data memory stores results of data processing performed by the processing element. The fill level unit generates a fill level signal signaling an amount of data stored in the data memory. The control unit controls processing power of the processing element based on the fill level signal.