Patents by Inventor Soethiha Soe

Soethiha Soe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190266337
    Abstract: Methods and apparatus for invoking a security feature of a computing device display in response to detecting an onlooker based on depth data are disclosed. An example apparatus includes an onlooker detector and a security manager. The onlooker detector is to detect an onlooker based on depth sensor data collected by a depth sensor associated with a computing device. The security manager is to automatically invoke a security feature of a display of the computing device in response to detection of the onlooker by the onlooker detector.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Uttam Sengupta, Soethiha Soe, Divyashree-Shivakumar Sreepathihalli
  • Publication number: 20190130639
    Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Soethiha Soe, Selva Panneer, Adam Lake, Nilesh Jain, Deepak Vembar, Glen J. Anderson, Varghese George, Carl Marshall, Scott Janus, Saurabh Tangri, Karthik Veeramani, Prasoonkumar Surti
  • Publication number: 20170153692
    Abstract: Techniques related to coordinating power management for multiple devices are discussed. Such techniques may include establishing communications between devices, inventorying the components of each device, and implementing a power management plan to eliminate any redundancy in the components and reduce the total power consumed by the devices.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Mark Yarvis, Samuel Benn, Soethiha Soe, Mark MacDonald, Dominic Fulginiti
  • Patent number: 9568972
    Abstract: Techniques related to coordinating power management for multiple devices are discussed. Such techniques may include establishing communications between devices, inventorying the components of each device, and implementing a power management plan to eliminate any redundancy in the components and reduce the total power consumed by the devices.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Mark Yarvis, Samuel Benn, Soethiha Soe, Mark MacDonald, Dominic Fulginiti
  • Patent number: 9354679
    Abstract: Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Robert Gough, Barnes Cooper, Basavaraj Astekar, Mazen Gedeon, Soethiha Soe
  • Patent number: 9345104
    Abstract: Systems and methods may provide for a power management apparatus including a first path to be coupled to an output of a narrow voltage direct current (NVDC) charger and an input of a backlight voltage regulator (VR). The apparatus may also include a second path to be coupled to an input of the NVDC charger and the input of the backlight voltage regulator, wherein the second path is to bypass current around the NVDC charger and to the input of the backlight VR if a voltage supplied by a first power source to the NVDC charger exceeds a voltage of a second power source coupled to the output of the NVDC. In one example, the first path includes a first diode and the second path includes a second diode, wherein the first and second diodes form an OR configuration for the apparatus between the first and second paths.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Soethiha Soe, Patrick K. Leung, Tod F. Schiff, Scot Lester
  • Patent number: 9274580
    Abstract: Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Ruoying Mary Ma, Craig Forbell, Soethiha Soe, Jawad Haj-Yihia, Jeffrey Carlson
  • Publication number: 20150323981
    Abstract: Techniques related to coordinating power management for multiple devices are discussed. Such techniques may include establishing communications between devices, inventorying the components of each device, and implementing a power management plan to eliminate any redundancy in the components and reduce the total power consumed by the devices.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Inventors: MARK YARVIS, SAMUEL BENN, SOETHIHA SOE, MARK MACDONALD, DOMINIC FULGINITI
  • Publication number: 20150277530
    Abstract: A system for dynamic power supply rail switching (DPRS), including a multi-rail power supply. The multi-rail power supply includes a main rail and a standby rail. The system for DPRS also includes a memory that is to store instructions and that is communicatively coupled to the multi-rail power supply. The system for DP RS also includes a processor communicatively coupled to the memory and the multi-rail power supply. Further, when the processor is to execute instructions, the multi-rail power supply will also supply power to the system, and in response to an entry condition being met, remove power from the main rail and leave the standby rail ON. Also, in response to an exit condition being met, the main rail powers on and starts to again supply power to the system.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: INTEL CORPORATION
    Inventors: VIDOOT PONNALA RATHNAKAR, PAUL M. ZAGACKI, SOETHIHA SOE, OHAD FALIK
  • Publication number: 20150264775
    Abstract: Systems and methods may provide for a power management apparatus including a first path to be coupled to an output of a narrow voltage direct current (NVDC) charger and an input of a backlight voltage regulator (VR). The apparatus may also include a second path to be coupled to an input of the NVDC charger and the input of the backlight voltage regulator, wherein the second path is to bypass current around the NVDC charger and to the input of the backlight VR if a voltage supplied by a first power source to the NVDC charger exceeds a voltage of a second power source coupled to the output of the NVDC. In one example, the first path includes a first diode and the second path includes a second diode, wherein the first and second diodes form an OR configuration for the apparatus between the first and second paths.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Inventors: Soethiha Soe, Patrick K. Leung, Tod F. Schiff, Scot Lester
  • Publication number: 20140189390
    Abstract: Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Robert Gough, Barnes Cooper, Basavaraj Astekar, Mazen Gedeon, Soethiha Soe
  • Publication number: 20140006833
    Abstract: Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Ruoying Mary Ma, Craig Forbell, Soethiha Soe, Jawad Haj-Yihia