Patents by Inventor Soh Yun Siah
Soh Yun Siah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11158646Abstract: A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.Type: GrantFiled: January 14, 2019Date of Patent: October 26, 2021Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventor: Soh Yun Siah
-
Patent number: 11119917Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.Type: GrantFiled: July 12, 2018Date of Patent: September 14, 2021Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Danny Pak-Chum Shum, Shyue Seng Tan, Xinshu Cai, Fan Zhang, Soh Yun Siah, Tze Ho Simon Chan
-
Patent number: 10608046Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.Type: GrantFiled: July 5, 2019Date of Patent: March 31, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
-
Publication number: 20200019500Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.Type: ApplicationFiled: July 12, 2018Publication date: January 16, 2020Inventors: Danny Pak-Chum SHUM, Shyue Seng TAN, Xinshu CAI, Fan ZHANG, Soh Yun SIAH, Tze Ho Simon CHAN
-
Publication number: 20190326352Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.Type: ApplicationFiled: July 5, 2019Publication date: October 24, 2019Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
-
Patent number: 10446607Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.Type: GrantFiled: December 28, 2016Date of Patent: October 15, 2019Assignee: GLOBALFOUNDARIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
-
Patent number: 10439129Abstract: One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.Type: GrantFiled: January 18, 2018Date of Patent: October 8, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Dimitri Houssameddine, Chenchen Jacob Wang, Bin Liu, Soh Yun Siah
-
Publication number: 20190221732Abstract: One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.Type: ApplicationFiled: January 18, 2018Publication date: July 18, 2019Inventors: Dimitri Houssameddine, Chenchen Jacob Wang, Bin Liu, Soh Yun Siah
-
Publication number: 20190148395Abstract: A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Inventor: Soh Yun Siah
-
Patent number: 10224338Abstract: A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.Type: GrantFiled: April 18, 2017Date of Patent: March 5, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventor: Soh Yun Siah
-
Publication number: 20180301464Abstract: A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.Type: ApplicationFiled: April 18, 2017Publication date: October 18, 2018Inventor: Soh Yun SIAH
-
Patent number: 10062641Abstract: Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.Type: GrantFiled: September 13, 2016Date of Patent: August 28, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Haifeng Sheng, Shifeng Zhao, Juan Boon Tan, Soh Yun Siah
-
Publication number: 20180182810Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
-
Publication number: 20180090505Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum, Pinghui Li, Zhiqiang Teo, Juan Boon Tan, Soh Yun Siah, Pey Kin Leong
-
Patent number: 9929165Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.Type: GrantFiled: September 28, 2016Date of Patent: March 27, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum, Pinghui Li, Zhiqiang Teo, Juan Boon Tan, Soh Yun Siah, Pey Kin Leong
-
Publication number: 20180076128Abstract: Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.Type: ApplicationFiled: September 13, 2016Publication date: March 15, 2018Inventors: Haifeng Sheng, Shifeng Zhao, Juan Boon Tan, Soh Yun Siah
-
Patent number: 9905282Abstract: Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.Type: GrantFiled: May 30, 2017Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Soh Yun Siah, Juan Boon Tan
-
Patent number: 9793208Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.Type: GrantFiled: September 29, 2015Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Haifeng Sheng, Juan Boon Tan, Wanbing Yi, Daxiang Wang, Soh Yun Siah
-
Publication number: 20170092584Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Haifeng SHENG, Juan Boon TAN, Wanbing YI, Daxiang WANG, Soh Yun SIAH
-
Patent number: 9236391Abstract: Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.Type: GrantFiled: June 8, 2015Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yu Chen, Huajun Liu, Siow Lee Chwa, Soh Yun Siah, Yanxia Shao, Yoke Leng Lim