Abstract: An integrated circuit can include frequency monitoring circuitry. The frequency monitoring circuitry may include a voltage based frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a first set of frequencies and a coarse frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a second set of frequencies different than the first set of frequencies. The voltage based frequency monitoring circuit can be configured to generate an output voltage having a first value when the input clock frequency is greater than a reference frequency and having a second value when the input clock frequency is less than the reference frequency. The coarse frequency monitoring circuit can include a reference counter and an input clock counter that generates a count value used to compute the input clock frequency.

Abstract: The present disclosure describes embodiments of a compact low voltage CMOS-based temperature sensor. The CMOS-based temperature sensor can include a reference voltage generator, a temperature front-end circuit, and an analog-to-digital converter (ADC). The reference voltage generator can be configured to generate a reference voltage independent of temperature. The temperature front-end circuit can include first and second transistors configured to generate a temperature signal proportional to temperature. The first MOS transistor can include first and second terminals. The first terminal can be electrically coupled to the reference voltage. The second terminal can be electrically coupled to the second MOS transistor. The second terminal can provide the temperature signal. The ADC can be electrically coupled to the reference voltage and configured to convert the temperature signal to a digital signal.

Abstract: A reference generator circuit included in a computer system may employ multiple field-effect transistors to generate a reference voltage whose value is based on the threshold voltages of the multiple field-effect transistors. The reference generator circuit can include a current source that generates a bias current. One of more stages included in the reference generator circuit can generate, using the bias current, respective output voltages whose values are based on differences in threshold voltages of field-effect transistors included in the stages. The output voltages can be combined to generate different reference voltage values.

Abstract: A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

Abstract: A power supply circuit included in a computer system regulates a power supply voltage using an input power supply. During startup, the power supply circuit uses a first reference voltage that is generated using the input power supply to regulated the power supply voltage. After a period of time has elapsed, the power supply circuit switches to using a more accurate second reference voltage that is generated using the regulated power supply voltage.

Abstract: Aspects of the disclosure are directed to a low power differential circuit. In accordance with one aspect, the low power differential circuit includes a crystal oscillator to generate a differential sinusoidal waveform, the crystal oscillator having a first terminal and a second terminal; a first capacitor coupled to the first terminal; a first inverter including a first input coupled to the first terminal and a first output coupled to the first capacitor; a second capacitor coupled to the second terminal; and a second inverter including a second input coupled to the second terminal and a second output coupled to the second capacitor, wherein the first inverter and the second inverter generate a synchronous square wave signal.

Abstract: A comparator circuit included in a computer system employs an inverter circuit as a high-speed comparison circuit. To allow the inverter circuit to compare an input signal to a particular threshold value, a trip point of the inverter circuit is adjusted to match the threshold value by modifying a voltage level of a power supply node coupled to the inverter. To modify the voltage level of the power supply node, a replica of the inverter circuit is biased to generate a bias signal that corresponds to the trip point of the inverter circuit. A comparator circuit compares the bias signal to the threshold value, and adjusts the voltage level of the power supply node using results of the comparison. An output circuit adjusts an output of the inverter circuit to generate a full-rail output signal.

Abstract: A power supply circuit included in a computer system is configured to generate a particular voltage level on a regulated power supply node using multiple charge pump circuits coupled together via a regulation device to provide regulation. A first charge pump circuit is configured to, using a voltage of an input power supply node, generate an intermediate voltage level, which is regulated by the regulation device. The second charge pump is configured to generate a voltage level on the regulated power supply node using a regulated version of intermediate voltage level. An impedance of the regulation device is adjusted using results of comparing the voltage level of the regulated power supply node to a reference voltage.

Abstract: A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

Abstract: A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

Abstract: Aspects of the disclosure are directed to a low power differential circuit. In accordance with one aspect, the low power differential circuit includes a crystal oscillator to generate a differential sinusoidal waveform, the crystal oscillator having a first terminal and a second terminal; a first capacitor coupled to the first terminal; a first inverter including a first input coupled to the first terminal and a first output coupled to the first capacitor; a second capacitor coupled to the second terminal; and a second inverter including a second input coupled to the second terminal and a second output coupled to the second capacitor, wherein the first inverter and the second inverter generate a synchronous square wave signal.

Abstract: Aspects of the present disclosure provide a low power differential frequency multiplier. An example frequency multiplier circuit generally includes a first set of transistors, a second set of transistors, and a resonant circuit. The first set of transistors comprises a first transistor and a second transistor, wherein each of the transistors in the first set is a first type of transistor. The second set of transistors comprises a third transistor and a fourth transistor, wherein each of the transistors in the second set is a second type of transistor. The resonant circuit has a first terminal coupled to the first set of transistors and a second terminal coupled to the second set of transistors, wherein the resonant circuit comprises an inductive element and a capacitive element coupled in parallel with the inductive element.

Abstract: A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

Abstract: Certain aspects of the present disclosure generally relate to a low-power relaxation oscillator. Certain aspects provide a circuit for generating an oscillating signal. The circuit generally includes a comparator, a first current source coupled to a reference potential node, a first resistive element coupled between the first current source and a voltage rail, a node between the first current source and the first resistive element being selectively coupled to a first input terminal of the comparator, a second current source coupled between a second input terminal of the comparator and the voltage rail, and a first capacitive element selectively coupled between the second input terminal of the comparator and the reference potential node.

Abstract: A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

Abstract: A Pierce oscillator is provided with a transconductance amplifier transistor having a DC drain voltage that is regulated to equal a reference voltage independently from a DC gate voltage for the transconductance amplifier transistor.

Abstract: A Pierce oscillator is provided with a transconductance amplifier transistor having a DC drain voltage that is regulated to equal a reference voltage independently from a DC gate voltage for the transconductance amplifier transistor.

Abstract: Disclosed is a low dropout (LDO) voltage regulator that includes a differential amplifier configured to amplify a differential between a reference voltage and a regulated output voltage, a pass transistor coupled to the differential amplifier and driven by an output of the differential amplifier, a compensation capacitor coupled to an output node of the differential amplifier, and an auxiliary amplifier, wherein an output node of the auxiliary amplifier is coupled to the compensation capacitor, and wherein an input node of the auxiliary amplifier is coupled to the pass transistor.

Abstract: Disclosed is a low dropout (LDO) voltage regulator that includes a differential amplifier configured to amplify a differential between a reference voltage and a regulated output voltage, a pass transistor coupled to the differential amplifier and driven by an output of the differential amplifier, a compensation capacitor coupled to an output node of the differential amplifier, and an auxiliary amplifier, wherein an output node of the auxiliary amplifier is coupled to the compensation capacitor, and wherein an input node of the auxiliary amplifier is coupled to the pass transistor.