Patents by Inventor Sohichiroh Kamei

Sohichiroh Kamei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5680156
    Abstract: A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane (60). The memory plane (60) comprises an input bus, an m.times.n array of memory cells (80) in communication with the input bus, and an m-bit-wide output bus. The array of memory cells (80) receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: October 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Robert John Gove, Keiichiroh Abe, Sohichiroh Kamei, Donald B. Doherty
  • Patent number: 5598188
    Abstract: A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane (60). The memory plane (60) comprises an input bus, an m.times.n array of memory cells (80) in communication with the input bus, and an m-bit-wide output bus. The array of memory cells (80) receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 28, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Robert J. Gove, Keiichiroh Abe, Sohichiroh Kamei, Donald B. Doherty