Abstract: A power exchange management device includes: a power consumer service processor that receives bid solicitation information from a power consumer, the bid solicitation information being for soliciting exchange of power; a prosumer service processor that publicizes a bid solicitation condition on a terminal device of a prosumer on the basis of the bid solicitation information and receives application information responding to the bid solicitation information from the terminal device of the prosumer; a prosumer power transmission information acquirer that acquires information about an amount of power transmitted to the grid by the power transmission facility of the prosumer by reverse power flow; and a target manager (24) that compares the acquired amount of transmitted power with a target value set on the basis of the bid solicitation information and the application information and determines an incentive to be offered to the prosumer depending on a result of the comparison.

Abstract: A symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection. The invention includes dividing plaintext composed of redundancy data and a message to generate plaintext blocks each having a predetermined length; generating a random number sequence based on a secret key, generating a random number block corresponding to one of the plaintext blocks from the random number sequence, outputting a feedback value obtained as a result of operation on the one plaintext block and the random number block, the feedback value being fed back for using the operation on another plaintext block, and performing an encryption operation using the one plaintext block, random number block, and feedback value.

Abstract: In a buffer and a state included in a pseudorandom number generating apparatus, the state has the configuration of assuming that the unit length of data processing is n, the state has a size of 3×n bits, and the buffer has a capacity of 32×n bits, and according to clock control, a state transformation section (state transformation function) for conducting a state alteration from time t to time t+1 uses a nonlinear function F (having an n-bit input and an n-bit output) twice, or two different nonlinear functions F and G respectively once. The state transformation section has such a configuration that a nonlinear function such as a round function of a block cipher sufficiently evaluated as to the cryptographic security and implementation.

Abstract: In a buffer and a state included in a pseudorandom number generating apparatus, the state has the configuration of assuming that the unit length of data processing is n, the state has a size of 3×n bits, and the buffer has a capacity of 32×n bits, and according to clock control, a state transformation section (state transformation function) for conducting a state alteration from time t to time t+1 uses a nonlinear function F (having an n-bit input and an n-bit output) twice, or two different nonlinear functions F and G respectively once. The state transformation section has such a configuration that a nonlinear function such as a round function of a block cipher sufficiently evaluated as to the cryptographic security and implementation.

Abstract: A symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection. The invention includes dividing plaintext composed of redundancy data and a message to generate plaintext blocks each having a predetermined length, generating a random number sequence based on a secret key, generating a random number block corresponding to one of the plaintext blocks from the random number sequence, outputting a feedback value obtained as a result of operation on the one plaintext block and the random number block, the feedback value being fed back for using in the operation on another plaintext block, and performing an encryption operation using the one plaintext block, random number block, and feedback value.

Abstract: A symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection. The invention includes dividing plaintext composed of redundancy data and a message to generate plaintext blocks each having a predetermined length; generating a random number sequence based on a secret key, generating a random number block corresponding to one of the plaintext blocks from the random number sequence, outputting a feedback value obtained as a result of operation on the one plaintext block and the random number block, the feedback value being fed back for using the operation on another plaintext block, and performing an encryption operation using the one plaintext block, random number block, and feedback value.

Abstract: An encryption system comprises a pseudo-random number generator (KS) for generating a long pseudo-random sequence (S) from a shorter encryption key (K) and, if necessary, a nonce value (N), and a mixing function (MX) for combining the sequence with a plaintext message (P) on a block-by-block basis, where successive blocks (S(i)) of 128 bits of the sequence are combined with successive 64-bit blocks of plaintext (P(i)) to produce successive 64-bit blocks of ciphertext. The blockwise use of a long pseudo-random sequence preserves the advantages of a block cipher in terms of data confidentiality and data integrity, as well as benefiting from the speed advantages of a stream cipher.

Abstract: A symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection. The invention includes dividing plaintext composed of redundancy data and a message to generate plaintext blocks each having a predetermined length, generating a random number sequence based on a secret key, generating a random number block corresponding to one of the plaintext blocks from the random number sequence, outputting a feedback value obtained as a result of operation on the one plaintext blocks and the random number block, the feedback value being fed back for using in the operation on another plaintext blocks, and performing an encryption operation using the one plaintext blocks, random number block, and feedback value.

Abstract: The random numbers are generated so as to perform an encryption processing and an authentication processing, thereby accomplishing an in-advance computation and a parallel computation. Also, the encryption processing and the authentication processing are performed, using the generated random numbers whose length is shorter than 2N with reference to the message length N. Concretely, the random numbers are generated using a pseudo random-number generator, and the generated random numbers are divided on each block basis. Also, a plaintext is divided on each block basis as well. Next, the exclusive-OR logical sums of random-number blocks Ri (1≦i≦N+1) and plaintext blocks Pi (1≦i≦N) are figured out, thereby acquiring ciphertext blocks Ci (1≦i≦N+2). Moreover, a hash function performs a key-accompanying input of the random-number blocks Ri (1≦i≦N+1), thereby generating the message authentication code of the generated ciphertext.

Abstract: Encrypting/decrypting conversion method and apparatus capable of controlling dynamically cyclic shift independent of data to undergo encrypting/decrypting conversion includes two or more different fixed circulating shift processing means for shifting cyclically the data by a fixed bit number leftward or rightward, a cyclic shift processing selecting means for selecting fixed cyclic shift processing means. The selecting sequence determined by the cyclic shift processing means is determined on the basis of data for determining the shift number selecting sequence.

Abstract: In a buffer and a state included in a pseudorandom number generating apparatus, the state has the configuration of assuming that the unit length of data processing is n, the state has a size of 3×n bits, and the buffer has a capacity of 32×n bits, and according to clock control, a state transformation section (state transformation function) for conducting a state alteration from time t to time t+1 uses a nonlinear function F (having an n-bit input and an n-bit output) twice, or two different nonlinear functions F and G respectively once. The state transformation section has such a configuration that a nonlinear function such as a round function of a block cipher sufficiently evaluated as to the cryptographic security and implementation.

Abstract: In a buffer and a state included in a pseudorandom number generating apparatus, the state has the configuration of assuming that the unit length of data processing is n, the state has a size of 3×n bits, and the buffer has a capacity of 32×n bits, and according to clock control, a state transformation section (state transformation function) for conducting a state alteration from time t to time t+1 uses a nonlinear function F (having an n-bit input and an n-bit output) twice, or two different nonlinear functions F and G respectively once. The state transformation section has such a configuration that a nonlinear function such as a round function of a block cipher sufficiently evaluated as to the cryptographic security and implementation.

Abstract: The present invention provides a symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection.

Abstract: The present invention provides a symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection.

Abstract: Encrypting/decrypting conversion method and apparatus capable of controlling dynamically cyclic shift independent of data to undergo encrypting/decrypting conversion includes two or more different fixed circulating shift processing means for shifting cyclically the data by a fixed bit number leftward or rightward, a cyclic shift processing selecting means for selecting fixed cyclic shift processing means. The selecting sequence determined by the cyclic shift processing means is determined on the basis of data for determining the shift number selecting sequence.