Abstract: Output signals of input buffers connected to the external input terminals of the semiconductor circuit are stored in respective memories. The memories are connected in series. Data of the memories are serially output from an external output terminal of the semiconductor circuit. In the above-mentioned operations, a pulse for storing the output signals of the input buffers into the memories, for selecting one of an output signal of the internal circuit and the data stored in the memories, and outputting the selected one from the external output terminal, is supplied via another external input terminal for a test. A pulse for connecting the memories in series is also supplied via a further external input terminal. The output signals of the input buffers can be output from the semiconductor circuit, without any operation of the internal circuit.

Abstract: A microprocessor having a register file inside is so combined with an external memory through a dedicated high-speed bus that the memory operates as a bank for said register file. This microprocessor further has means for controlling a data transfer with said memory or peripheral devices. When an address information to access said memory is input to this microprocessor in order to control a data transfer between said memory and a peripheral device, said control means finds if the accessed area in said memory is now in use as a bank for said register file, or not. When it is in use, said control means controls a data transfer between said peripheral device and said register file, instead of controlling the data transfer between said memory and said peripheral device. So, said peripheral device can always access the newest information in said memory.

Abstract: A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a plurality of bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory, such as a built-in read only memory (ROM), for storing a user program. The processor further includes a bank structured memory, connected to the CPU via an exclusive-use data bus, for holding data stored in the data memories using the bank specifying registers and for returning data stored in the bank structural memory to the data memories using the bank specifying registers.

Abstract: A logical circuit is tested by comparing at least one arbitrary bit of a logical signal among logical signals outputted from the logical circuit with an expected value corresponding to the correct level of the logical signal, and comparing a bit position at which the level of the logical signal changes with an expected change point indicating a bit position at which the level of the correct logical signal changes.

Abstract: A plurality of semiconductor integrated circuit devices are mounted on a film carrier. First electrical connecting sections and first electrical wiring sections for electrically connecting the first electrical connecting sections to the semiconductor integrated circuit devices are provided on the film carrier. Second and third electrical connecting sections and second electrical wiring sections are provided on a film-like probe for electrical characteristic test. The second electrical connecting sections are provided in position corresponding to the first electrical connecting sections of the film carrier. The third electrical connecting sections are used to supply electrical signals to the exterior or derive an electrical signal to the exterior and check the electrical signal. The second electrical wiring sections electrically connects the second and third electrical connecting sections to each other.

Abstract: A plurality of semiconductor integrated circuit devices are mounted on a film carrier. First electrical connecting sections and first electrical wiring sections for electrically connecting the first electrical connecting sections to the semiconductor integrated circuit devices are provided on the film carrier. Second and third electrical connecting sections and second electrical wiring sections are provided on a film-like probe for electrical characteristic test. The second electrical connecting sections are provided in position corresponding to the first electrical connecting sections of the film carrier. The third electrical connecting sections are used to supply electrical signals to the exterior or derive an electrical signal to the exterior and check the electrical signal. The second electrical wiring sections connects the second and third electrical connecting sections to each other.

Abstract: A multifunctional scan flip-flop having a normal function and a scan function, including: a first latch used for a normal function for latching input data applied to a data input terminal during a normal function operation, the latch operation being carried out synchronous with a clock applied to a clock input terminal; a second latch used for a scan function for holding scan data applied to a scan data input terminal during a scan function operation; and a delay circuit for delaying one of the input data and the clock relative to the other, the delay operation being carried out in accordance with the H/L level of the scan data held by the second latch.

Abstract: The input nodes and output nodes of a plurality of storing circuits for storing plural-bit data are connected to one another to constitute a shift register. Each of the plurality of storing circuits includes a selection circuit for selecting 1-bit data from the plural-bit data according to a selection signal, a first latch circuit for latching the 1-bit data selected by the selection circuit in synchronism with a first clock signal, and a number of second latch circuits, which number corresponds to the number of bits of input data, for latching an output of the first latch circuit in synchronism with a plurality of second clock signals having phases different from that of the first clock signal. Data sequentially selected by the selection circuit is latched into the first latch circuit and then sequentially latched into the second latch circuit in a time-sharing fashion.