Patents by Inventor Somasunder Kattepura Sreenath
Somasunder Kattepura Sreenath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9465759Abstract: Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first plurality of data flip-flops coupled to a data lookup circuit of a SerDes interface; a second plurality of data flip-flops coupled to the data lookup circuit; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.Type: GrantFiled: July 17, 2014Date of Patent: October 11, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Somasunder Kattepura Sreenath, Gururaj Kulkarni, Chandan Muddamsetty, Pradeep Kumar Ubbala
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Publication number: 20160019174Abstract: Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first plurality of data flip- flops coupled to a data lookup circuit of a SerDes interface; a second plurality of data flip-flops coupled to the data lookup circuit; a plurality of latches, each latch of the plurality of latches coupled to a corresponding data flip-flop of the second plurality of data flip-flops; and a plurality of multiplexers coupled to the plurality of latches, to the first plurality of data flip-flops, and to a transmitter circuit.Type: ApplicationFiled: July 17, 2014Publication date: January 21, 2016Inventors: Somasunder Kattepura Sreenath, Gururaj Kulkarni, Chandan Muddamsetty, Pradeep Kumar Ubbala
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Patent number: 9065430Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.Type: GrantFiled: April 22, 2014Date of Patent: June 23, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sumantra Seth, Somasunder Kattepura Sreenath, Sujoy Chinmoy Chakravarty, Arakali Abhijith
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Publication number: 20140247071Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.Type: ApplicationFiled: April 22, 2014Publication date: September 4, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sumantra Seth, Somasunder Kattepura Sreenath, Sujoy Chinmoy Chakravarty, Arakali Abhijith
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Patent number: 8704550Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.Type: GrantFiled: November 29, 2007Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Sumantra Seth, Somasunder Kattepura Sreenath, Sujoy Chakravarty, Abhijith Arakali
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Patent number: 8054103Abstract: A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.Type: GrantFiled: October 22, 2010Date of Patent: November 8, 2011Assignee: Texas Instruments IncorporatedInventors: Jayawardan Janardhanan, Gopalkrishna Ullal Nayak, Vikas Kumar Sinha, Sujoy Chakravarty, Shivaprakash Halagur, Somasunder Kattepura Sreenath
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Publication number: 20090140772Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Inventors: Sumantra Seth, Somasunder Kattepura Sreenath, Sujoy Chakravarty, Abhijith Arakali
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Patent number: 7522003Abstract: A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element.Type: GrantFiled: December 26, 2006Date of Patent: April 21, 2009Assignee: Texas Instruments IncorporatedInventors: Sumantra Seth, Somasunder Kattepura Sreenath
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Publication number: 20080150638Abstract: A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: SUMANTRA SETH, Somasunder Kattepura Sreenath
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Patent number: 7332965Abstract: A gate leakage insensitive current mirror circuit including an input stage, an output stage, and a pair of complementary source followers. The pair of complementary source followers is connected between the input stage and the output stage. In operation, the input stage receives an input current and the pair of complementary source followers receives a first current source and a second current source. The output stage then provides an output current. The complementary source followers form a negative feedback loop and establish a bias voltage for the input stage and the output stage as a function of the input current that is independent of gate leakage between the input stage and the output stage.Type: GrantFiled: April 19, 2006Date of Patent: February 19, 2008Assignee: Texas Instruments IncorporatedInventors: Sumantra Seth, Somasunder Kattepura Sreenath