Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.

Abstract: A data storage device includes a memory array for storing data; a host interface for providing an interface with a host computer running an application; a central control unit configured to receive a command in a submission queue from the application and initiate a search process in response to a search query command; a preprocessor configured to reformat data contained in the search query command and generate a reformatted data; and one or more data processing units configured to extract one or more features from the reformatted data and perform a data operation on the data stored in the memory array in response to the search query command and return matching data from the data stored in the memory array to the application via the host interface.

Abstract: A data storage device includes a memory array for storing data; a host interface for providing an interface with a host computer running an application; a central control unit configured to receive a command in a submission queue from the application and initiate a search process in response to a search query command; a preprocessor configured to reformat data contained in the search query command and generate a reformatted data; and one or more data processing units configured to extract one or more features from the reformatted data and perform a data operation on the data stored in the memory array in response to the search query command and return matching data from the data stored in the memory array to the application via the host interface.

Abstract: A method includes: receiving a Transmission Control Protocol (TCP)/Internet Protocol (IP) packet from an initiator, wherein the TCP/IP packet includes an IP address of a switch and a port number; looking up an address translation table based on the IP address of the switch and the port number; translating the IP address of the switch to a private IP address based on the port number according to address mapping information stored in the address translation table; and routing the TCP/IP packet to a non-volatile memory express over fabrics (NVMeoF) device having the private IP address. A network address translation (NAT) router implemented in the switch is configured to perform the address translation from the IP address of the switch to the private IP address of the NVMeoF device.

Abstract: A data replication system has a chassis including a plurality of eSSDs, a fabrics switch, and a baseboard management controller (BMC). The BMC configures one of the plurality of eSSDs as an active eSSD and one or more of the plurality of eSSDs as one or more passive eSSDs. The fabrics switch of the chassis is programmed to forward packets destined for the active eSSD to both the active eSSD and the one or more passive eSSDs. In response to a host data write command received from the host, the active eSSD stores the host data and sends an address and an instruction corresponding to the host data to the one or more passive eSSDs. Each of the one or more passive eSSDs stores a copy of the host data using the address and the instruction received from the active eSSD and the host data received in the packets forwarded by the fabrics switch.

Abstract: A data replication system has a chassis including a plurality of eSSDs, a fabrics switch, and a baseboard management controller (BMC). The BMC configures one of the plurality of eSSDs as an active eSSD and one or more of the plurality of eSSDs as one or more passive eSSDs. The fabrics switch of the chassis is programmed to forward packets destined for the active eSSD to both the active eSSD and the one or more passive eSSDs. In response to a host data write command received from the host, the active eSSD stores the host data and sends an address and an instruction corresponding to the host data to the one or more passive eSSDs. Each of the one or more passive eSSDs stores a copy of the host data using the address and the instruction received from the active eSSD and the host data received in the packets forwarded by the fabrics switch.

Abstract: A data storage device includes a memory array for storing data; a host interface for providing an interface with a host computer running an application; a central control unit configured to receive a command in a submission queue from the application and initiate a search process in response to a search query command; a preprocessor configured to reformat data contained in the search query command and generate a reformatted data; and one or more data processing units configured to extract one or more features from the reformatted data and perform a data operation on the data stored in the memory array in response to the search query command and return matching data from the data stored in the memory array to the application via the host interface.

Abstract: A method includes: receiving a Transmission Control Protocol (TCP)/Internet Protocol (IP) packet from an initiator, wherein the TCP/IP packet includes an IP address of a switch and a port number; looking up an address translation table based on the IP address of the switch and the port number; translating the IP address of the switch to a private IP address based on the port number according to address mapping information stored in the address translation table; and routing the TCP/IP packet to a non-volatile memory express over fabrics (NVMeoF) device having the private IP address. A network address translation (NAT) router implemented in the switch is configured to perform the address translation from the IP address of the switch to the private IP address of the NVMeoF device.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

Abstract: A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. If X16 or X32 memory devices are implemented, a technique for striping the data from each memory device is implemented to detect errors in the X16 and X32 devices.

Abstract: A computer system includes a plurality of field replaceable units, each having volatile memory and at least one CPU. The FRUs communicate with each other via centralized logic. A RAID data fault tolerance technique is applied to the system so that an FRU can be lost or removed without loss of its data. An exclusive OR engine is included in the centralized logic or distributed among the FRUs. The RAID logic can restripe itself upon removal or addition of a FRU.

Abstract: A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Abstract: An electronic system embodies a security system which provides varying levels of security based on the location of the system. As such, the system includes a location module, such as a geosynchronous positioning system (“GPS”) receiver that permits the system to determine its location relative to a plurality of preset location areas. Such location areas might be programmed to include the user's office, home, predetermined location for a business trip and the like. Based on the location area in which the system is located, the system invokes a security mode associated with that particular location area. Different location areas may have different security modes.

Abstract: A method and apparatus for detecting the presence of hot-pluggable components in a computer system. The method and apparatus includes an electromagnetic energy source located on a first side of a system board proximate an edge connector, the electromagnetic energy source for generating electromagnetic energy directed at least toward a second opposing side of the system board. The method and apparatus further includes an electromagnetic energy detector located on the second side of the system board, the electromagnetic energy detector for detecting a presence of electromagnetic energy when a hot-pluggable component is not mated to the edge connector and the electromagnetic energy is thereby unobstructed by the hot-pluggable component, the electromagnetic energy detector further for detecting an absence of electromagnetic energy when the hot-pluggable component is mated to the edge connector and the electromagnetic energy is thereby obstructed by the hot-pluggable component.

Abstract: A computer network employs a fault-tolerant or redundant switch architecture. The network includes redundant data paths coupling end nodes and switches. Fault-tolerant repeaters (FTRs) can be stand-alone devices or can be incorporated into the switches. Using error detection, the FTR checks to see if the data is good on all paths. If the data received on one path is “bad” and the data is “good” on another path, the FTR transmits the “good” data in place of the “bad” data. For any switch, a pair of incoming ports may be configured as redundant incoming ports and a pair of outgoing ports may be configured as redundant outgoing ports.

Abstract: A core logic chipset for a computer system is provided which can be configured as a bridge between either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chipset and either an AGP or PCI device(s). The common bus, which is part of a fault-tolerant interconnect system, includes a first bus portion and a lower bus portion. When an error (e.g., a parity error) is detected on the first bus portion, the transaction is transferred over the second bus portion. When an error is detected on the second bus portion, the transaction is transferred over the first bus portion. If errors are detected on both portions, the transaction may be terminated.

Abstract: A computer system with a plurality of peripheral busses is adapted to permit multicast signals to be transmitted by a device on one peripheral bus to multiple devices on the other peripheral bus. In an exemplary embodiment, two PCI busses are provided, and master devices on either bus are capable of transmitting multicast signals to multiple targets on either bus. Targets of a multicast cycle are identified by a target identification signal on a first and a second multicast bus. A bus bridge relays the data for the multicast cycle between devices. In an exemplary embodiment, a sideband signal from the master to the bridge indicates a multicast signal has been transmitted on one of the PCI busses. In response, the bridge relays the multicast data to the second PCI bus, while also transmitting a sideband signal to devices on the second bus indicating multicast data is being transmitted on that bus. Targets identified on the second bus then capture the multicast data.

Abstract: A computer system includes multiple controllers that assist in executing the Power-On Self Test (POST) sequence to minimize the time required to complete system initialization. By shifting some of the responsibilities for executing the POST sequence to other controllers within the system, the testing and initialization of system devices can proceed concurrently. The controllers interface with peripheral devices, and include a register set that includes command information for initializing the testing and initialization of associated peripherals. The register set also includes dedicated bits for indicating the status of testing and initialization cycles, which can be read by the CPU to determine if testing or initialization is in progress, if it has completed, and if any errors have occurred. The register set also includes a configuration register for indicating configuration information and operating parameters of the initialized drive or peripheral.

Abstract: A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.