Abstract: A method for automatically sending containment instructions from a central containment component contained in a public cloud to an endpoint contained inside a company network where a malicious activity has been detected. The method includes a central containment component elaborating and placing a secured containment instruction inside a messaging queue of the central containment component, and a component, called edge containment component, running inside the company network, periodically polling the messaging queue service by creating an outgoing connection from the company network to the central containment component in the public cloud. When the edge containment component detects the containment instruction, the edge containment component retrieves, decodes and sends the containment instruction to the endpoint inside the company network.

Abstract: This application relates generally to computer-implemented methods and systems for computer graphics processing. Specifically, the application involves automatically selecting and blending images based on image aesthetic scores. Computer systems are provided that may blend an automatically selected foreground image with an automatically selected background image to produce an editable photo creation.

Abstract: This application relates generally to computer-implemented methods and systems for computer graphics processing. Specifically, the application involves automatically selecting and blending images based on image aesthetic scores. Computer systems are provided that may blend an automatically selected foreground image with an automatically selected background image to produce an editable photo creation.

Abstract: An apparatus includes a plurality of mirrored transistor pairs configured to provide a first output current, and a second output current that is substantially equal to the first output current. The apparatus also includes a load isolation transistor configured to pass the first output current along to a resistive load and a first and a second biasing transistor configured to bias the load isolation transistor with a load biasing voltage. A gate and drain of the second biasing transistor may be connected to a gate of the load isolation transistor and a drain of the first biasing transistor. Furthermore, a source of the second biasing transistor may be connected to a gate of the first biasing transistor. The width-to-length ratio of the load isolation transistor, the first biasing transistor, and the second biasing transistor are selected to eliminate PTAT dependencies in the first output current.

Abstract: An apparatus includes a plurality of mirrored transistor pairs configured to provide a first output current, and a second output current that is substantially equal to the first output current. The apparatus also includes a load isolation transistor configured to pass the first output current along to a resistive load and a first and a second biasing transistor configured to bias the load isolation transistor with a load biasing voltage. A gate and drain of the second biasing transistor may be connected to a gate of the load isolation transistor and a drain of the first biasing transistor. Furthermore, a source of the second biasing transistor may be connected to a gate of the first biasing transistor. The width-to-length ratio of the load isolation transistor, the first biasing transistor, and the second biasing transistor are selected to eliminate PTAT dependencies in the first output current.

Abstract: An apparatus includes a plurality of mirrored transistor pairs configured to provide a first output current, and a second output current that is substantially equal to the first output current. The apparatus also includes a load isolation transistor configured to pass the first output current along to a resistive load and a first and a second biasing transistor configured to bias the load isolation transistor with a load biasing voltage. A gate and drain of the second biasing transistor may be connected to a gate of the load isolation transistor and a drain of the first biasing transistor. Furthermore, a source of the second biasing transistor may be connected to a gate of the first biasing transistor. The width-to-length ratio of the load isolation transistor, the first biasing transistor, and the second biasing transistor are selected to eliminate PTAT dependencies in the first output current.