Patents by Inventor Song Quan Shang

Song Quan Shang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9306780
    Abstract: A transceiver includes a transmitter and a receiver. The transmitter includes a precoder stage, an encoder stage and a first converter stage. The precoder stage receives an input binary signal and a previously processed binary signal. The encoder stage is electrically coupled to the precoder stage and the first converter stage and includes a feed forward equalizer (FFE). The first converter stage generates a modulated signal. The receiver includes a second converter stage, an amplifier stage, a first equalizer stage and a second equalizer stage. The second converter stage receives the modulated signal. The first equalizer stage is electrically coupled to the amplifier stage. The second equalizer stage is electrically coupled to the first equalizer stage. The second equalizer stage includes a decision feedback equalizer (DFE) that converts the modulated signal into an output binary signal.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 5, 2016
    Assignee: SEMTECH CORPORATION
    Inventor: Song Quan Shang
  • Publication number: 20140255037
    Abstract: A transceiver includes a transmitter and a receiver. The transmitter includes a precoder stage, an encoder stage and a first converter stage. The precoder stage receives an input binary signal and a previously processed binary signal. The encoder stage is electrically coupled to the precoder stage and the first converter stage and includes a feed forward equalizer (FFE). The first converter stage generates a modulated signal. The receiver includes a second converter stage, an amplifier stage, a first equalizer stage and a second equalizer stage. The second converter stage receives the modulated signal. The first equalizer stage is electrically coupled to the amplifier stage. The second equalizer stage is electrically coupled to the first equalizer stage. The second equalizer stage includes a decision feedback equalizer (DFE) that converts the modulated signal into an output binary signal.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: SEMTECH CORPORATION
    Inventor: Song Quan Shang
  • Patent number: 7587145
    Abstract: An optical to electrical converter is to receive an incoming optical data communications signal. A binary to ternary encoder has an input coupled to an output of the converter. A ternary to binary decoder has first and second limiting amplifiers, each having a pair of complementary inputs. One of the inputs of each pair is coupled to a first adjustable threshold circuit and the other is coupled to an output of the encoder. A logical summing circuit has a pair of inputs coupled to outputs of the first and second limiting amplifiers, respectively. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: Song Quan Shang, Craig Schulz, Tom Mader
  • Patent number: 7574145
    Abstract: An optoelectronic circuit has an optical to electrical converter, a duo-binary encoder with an input coupled to an output of the converter, and a duo-binary decoder having an input coupled to the output of the encoder. A decision circuit having an input coupled to an output of the decoder is also provided. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: August 11, 2009
    Assignee: Intel Corporation
    Inventors: Craig Schulz, Tom Mader, Song Quan Shang
  • Publication number: 20080002985
    Abstract: An optical to electrical converter is to receive an incoming optical data communications signal. A binary to ternary encoder has an input coupled to an output of the converter. A ternary to binary decoder has first and second limiting amplifiers, each having a pair of complementary inputs. One of the inputs of each pair is coupled to a first adjustable threshold circuit and the other is coupled to an output of the encoder. A logical summing circuit has a pair of inputs coupled to outputs of the first and second limiting amplifiers, respectively. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 3, 2008
    Inventors: Song Quan Shang, Craig Schulz, Tom Mader