Abstract: A cold shrinkable termination for an electric power cable that includes an insulation tube and stress control glue. When the cold shrinkable termination is mounted on the electric power cable, the stress control glue fills a gap between the electric power cable and the insulation tube so as to prevent local electric field concentration from occurring at an exposed end of the electric power cable. The stress control glue has a dielectric constant within a range of 5 to 100. In this cold shrinkable termination, a stress control glue with high dielectric constant is provided to optimize the electric-field distribution on an insulation surface of the electric power cable. Thereby, the structure of the cold shrinkable termination is simplified and the cost thereof is reduced. The cold shrinkable termination may be adapted to an electric power cable used to transmit voltage less than 26/35 kV.

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract: Methods and systems for increasing the effective dynamic range of an image sensor are disclosed. Each pixel in the sensor is exposed for a respective first exposure time. Each pixel's response to the respective first exposure is measured and compared to threshold values. Based on the pixel's response to the respective first exposure time, an optimal exposure is calculated for each pixel. The optimal exposure time is applied to each pixel by utilizing row-enabled and column-enabled signals at each pixel within the sensor.

Abstract: A method of producing bit-patterned media is provided whereby a shell structure is added on a bit-patterned media dot. The shell may be an antiferromagnetic material that will help stabilize the magnetization configuration at the remanent state due to exchange coupling between the dot and its shell. Therefore, this approach also improves the thermal stability of the media dot and helps each individual media dot maintain a single domain state.

Abstract: An image sensor that includes a pixel array with image pixels with conditional reset circuitry. The pixels can be reset by a combination of row select and column reset signals, which implements the reset function while minimizing the number of extra signal lines. The pixels may also include pinned photodiodes. The manner in which the pinned photodiodes are used reduces noise and allows the quantization of the pixel circuits to be programmable.

Abstract: A method of producing bit-patterned media is provided whereby a shell structure is added on a bit-patterned media dot. The shell may be an antiferromagnetic material that will help stabilize the magnetization configuration at the remanent state due to exchange coupling between the dot and its shell. Therefore, this approach also improves the thermal stability of the media dot and helps each individual media dot maintain a single domain state.

Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

Abstract: An analog multiplexer is configured to multiplex a plurality of input analog signal channels into a single output analog signal channel. The analog multiplexer comprises a plurality of input sampling circuits associated with respective ones of the input analog signal channels and an amplifier having an input controllably connectable in turn to each of the input sampling circuits. The analog multiplexer is further configured to connect at least a given one of the input analog signal channels to a sampling element of its corresponding input sampling circuit at a predetermined time prior to connecting the sampling element of that input sampling circuit to the input of the amplifier. The predetermined time is less than a full clock cycle of a sampling clock of the amplifier. The analog multiplexer may be implemented in readout circuitry coupled to a pixel array in an image sensor.

Abstract: The present invention provides an efficient, safe and cost effective way to prepare 5-(4-methyl-1H-imidazol-1-yl)-3-(trifluoromethyl)-benzenamine which is a key intermediate for the preparation of substituted pyrimidinylaminobenzamides of formula (II):

Abstract: Embodiments of the invention provide a multi-terminal resistance device with first and second electrodes, a shared third electrode, and a resistance layer providing first and second current paths between the shared third electrode and the first and second electrodes, respectively. A current state of the device may be programmed by applying one or more electrical signals along the first and/or second current paths to change a resistance of the device. In some embodiments, applying an electrical signal may switch a junction resistance of the first and/or second electrodes and the resistance layer between two or more resistance values. The device may include a shared fourth electrode to provide extra programming capability. In some embodiments, the device may be used to store a data state, to determine a count of multiple electrical signals, or to perform a logic operation between two electrical signals.

Abstract: A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode.

Abstract: A magnetic sensor includes a sensor stack having a first magnetic portion, a second magnetic portion, and a barrier layer between the first magnetic portion and the second magnetic portion. At least one of the first magnetic portion and the second magnetic portion includes a multilayer structure having a first magnetic layer having a positive magnetostriction adjacent to the barrier layer, a second magnetic layer, and an intermediate layer between the first magnetic layer and the second magnetic layer. The magnetic sensor has an MR ratio of at least about 80% when the magnetic sensor has a resistance-area (RA) product of about 1.0 ?·?m2.

Abstract: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip.

Abstract: Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.

Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.

Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

Abstract: The present invention provides an efficient, safe and cost effective way to prepare 5-(4-methyl-1H-imidazol-1-yl)-3-(trifluoromethyl)-benzenamine which is a key intermediate for the preparation of substituted pyrimidinylaminobenzamides of formula (II):

Abstract: A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode.