Patents by Inventor Songkram Srivathanakul
Songkram Srivathanakul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200111704Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of gate structures above a semiconductor substrate, wherein a plurality of cavities are defined between adjacent gate structures, and performing a first atomic layer deposition process to form a first stressed dielectric layer in the plurality of cavities and define a first seam in each cavity of the plurality of cavities, each first seam having a height greater than a height of the adjacent gate structures.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Eric S. Kozarksy, Hong Yu, Songkram Srivathanakul, Jiehui Shu, Jinping Liu, Bryan Rice
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Patent number: 9905460Abstract: A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.Type: GrantFiled: November 5, 2015Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Moosung M. Chae, Ki Young Lee, Songkram Srivathanakul
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Publication number: 20180005893Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate. A patterned mask layer is formed above the process layer. The patterned mask layer includes first openings exposing portions of the process layer. A carbon-containing silicon dioxide layer is formed above the patterned mask layer and in the first openings. The carbon-containing silicon dioxide layer is planarized to remove portions extending outside the first openings and generate a plurality of mask elements from remaining portions of the carbon-containing silicon dioxide layer. The patterned mask layer is removed. The process layer is etched using the mask elements as an etch mask.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Inventors: Huy Cao, Huang Liu, Guillaume Bouche, Songkram Srivathanakul
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Publication number: 20170338325Abstract: We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer; and an ultraviolet (UV) cured high density plasma (HDP) nitride cap layer in the gate structure cavity above the at least one metal layer. We also disclose at least one method and at least one system by which the semiconductor device may be formed. The UV cured HDP nitride cap layer may be substantially free of voids or seams, and as a result, the semiconductor device may have a reduced Vt shift relative to comparable semiconductor devices known in the art.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Chih-Chiang Chang, Katsunori Onishi, Songkram Srivathanakul
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Patent number: 9793169Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.Type: GrantFiled: June 7, 2016Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Huy Cao, Huang Liu, Guillaume Bouche, Songkram Srivathanakul
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Publication number: 20170133325Abstract: A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern within a remaining portion of the dielectric layer. A metal liner layer is disposed on a surface of the pattern to provide a metal lined pattern. A metal filling is disposed over the metal lined pattern, the metal filling being at least partially composed of a metal used in the metal liner layer. Diffusion ions are disposed in one of the metal filling and the metal liner layer. Heat is applied to the metal filling and metal liner layer to diffuse the diffusion ions from one of the metal filling and the metal liner layer into the dielectric layer to form a barrier layer between the metal liner layer and the dielectric layer.Type: ApplicationFiled: November 5, 2015Publication date: May 11, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Moosung M. CHAE, Ki Young LEE, Songkram SRIVATHANAKUL
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Patent number: 9349814Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: GrantFiled: June 4, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
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Patent number: 9330982Abstract: A method of forming a diffusion barrier film over fins and the resulting device are provided. Embodiments include forming silicon fins over a substrate; depositing a borosilicate glass (BSG) liner cap over a first set of the silicon fins; depositing a phosphosilicate (PSG) liner cap over a second set of the silicon fins; and depositing a silicon oxycarbide (SiOC) diffusion barrier film over the BSG and PSG liner caps.Type: GrantFiled: August 14, 2015Date of Patent: May 3, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Songkram Srivathanakul, Jinping Liu, In Soo Jung
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Patent number: 9318440Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.Type: GrantFiled: July 14, 2015Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Songkram Srivathanakul, Huang Liu, Garo Jacques Derderian, Boaz Alperson
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Patent number: 9245979Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.Type: GrantFiled: May 24, 2013Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Xiuyu Cai, Ruilong Xie, Songkram Srivathanakul
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Publication number: 20150357285Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.Type: ApplicationFiled: July 14, 2015Publication date: December 10, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Huy CAO, Songkram SRIVATHANAKUL, Huang LIU, Garo Jacques DERDERIAN, Boaz ALPERSON
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Publication number: 20150270364Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: ApplicationFiled: June 4, 2015Publication date: September 24, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Tsung-Liang CHEN, Hung-Wei LIU, Rohit PAL, Hsin-Neng TAI, Huey-Ming WANG, Tae Hoon LEE, Songkram SRIVATHANAKUL, Danni CHEN
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Patent number: 9130019Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.Type: GrantFiled: January 8, 2014Date of Patent: September 8, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Songkram Srivathanakul, Huang Liu, Garo Jacques Derderian, Boaz Alperson
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Patent number: 9093560Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: GrantFiled: September 20, 2013Date of Patent: July 28, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
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Publication number: 20150194342Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.Type: ApplicationFiled: January 8, 2014Publication date: July 9, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Huy CAO, Songkram SRIVATHANAKUL, Huang LIU, Garo Jacques DERDERIAN, Boaz ALPERSON
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Publication number: 20150084131Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Inventors: Tsung-Liang CHEN, Hung-Wei LIU, Rohit PAL, Hsin-Neng TAI, Huey-Ming WANG, Tae Hoon LEE, Songkram SRIVATHANAKUL, Danni CHEN
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Patent number: 8940650Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.Type: GrantFiled: March 6, 2013Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan
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Patent number: 8900940Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.Type: GrantFiled: January 10, 2013Date of Patent: December 2, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Ashish K. Jha, Tae-Hoon Kim, Tae Hoon Lee, Chang Ho Maeng, Songkram Srivathanakul, Haiting Wang
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Publication number: 20140346599Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.Type: ApplicationFiled: May 24, 2013Publication date: November 27, 2014Applicant: GLOBALFOUNDRIES, Inc.Inventors: Xiuyu Cai, Ruilong Xie, Songkram Srivathanakul
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Publication number: 20140256141Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan