Patents by Inventor Sonja Koller
Sonja Koller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11877403Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.Type: GrantFiled: September 27, 2021Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
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Patent number: 11784143Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.Type: GrantFiled: May 23, 2019Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Sonja Koller, Kilian Roth, Josef Hagn, Andreas Wolter, Andreas Augustin
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Publication number: 20230317544Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.Type: ApplicationFiled: March 21, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230317551Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Vishnu Prasad, Abdallah Bacha, Mohan Prashanth Javare Gowda, Lizabeth Keser, Thomas Wagner, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz
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Publication number: 20230317681Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Sonja Koller, Vishnu Prasad, Bernd Waidhas, Eduardo De Mesa, Lizabeth Keser, Thomas Wagner, Mohan Prashanth Javare Gowda, Abdallah Bacha, Jan Proschwitz
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Publication number: 20230298953Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.Type: ApplicationFiled: March 20, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Pouya Talebbeydokhti, Mohan Prashanth Javare Gowda, Sonja Koller, Stephan Stoeckl, Thomas Wagner, Wolfgang Molzer
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Publication number: 20230300975Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230299043Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Sonja Koller, Jan Proschwitz, Eduardo De Mesa
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Patent number: 11764187Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.Type: GrantFiled: September 29, 2017Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
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Publication number: 20230282546Abstract: Embodiments of a microelectronic assembly comprise an integrated circuit (IC) die and a package substrate having a core and redistribution layers on either side of the core. The IC die is coupled to a face of the package substrate, the face being parallel to the core. The core comprises one of glass, ceramic, and metal. The redistribution layers comprise one or more layers of a dielectric material, with conductive traces adjacent to the one or more layers of the dielectric material and conductive vias through the one or more layers of the dielectric material. The core comprises a hollow channel.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Sonja Koller, Jan Proschwitz, Eduardo De Mesa
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Publication number: 20230282615Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Thomas Wagner, Abdallah Bacha, Vishnu Prasad, Mohan Prashanth Javare Gowda, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz, Lizabeth Keser
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Publication number: 20230268286Abstract: Embodiments of a microelectronic assembly comprise a package substrate, including: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer, and the third layer comprises a second material different from the first material.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Applicant: Intel CorporationInventors: Mohan Prashanth Javare Gowda, Stephan Stoeckl, Thomas Wagner, Sonja Koller, Wolfgang Molzer, Pouya Talebbeydokhti
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Publication number: 20230268291Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Applicant: Intel CorporationInventors: Mohan Prashanth Javare Gowda, Stephan Stoeckl, Sonja Koller, Wolfgang Molzer, Thomas Wagner, Pouya Talebbeydokhti
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Patent number: 11646498Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.Type: GrantFiled: May 16, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Kilian Roth, Sonja Koller, Josef Hagn, Andreas Wolter, Andreas Augustin
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Patent number: 11456116Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.Type: GrantFiled: March 30, 2017Date of Patent: September 27, 2022Assignee: Intel CorporationInventors: Andreas Augustin, Bernd Waidhas, Sonja Koller, Reinhard Mahnkopf, Georg Seidemann
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Publication number: 20220294115Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.Type: ApplicationFiled: June 2, 2022Publication date: September 15, 2022Inventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoecki, Thomas Wagner, Josef Hagn
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Patent number: 11410908Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.Type: GrantFiled: June 26, 2018Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Reinhard Mahnkopf, Sonja Koller, Andreas Wolter
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Patent number: 11374323Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.Type: GrantFiled: March 31, 2017Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Andreas Augustin, Sonja Koller, Bernd Waidhas, Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner, Josef Hagn
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Publication number: 20220015244Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
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Patent number: 11145577Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.Type: GrantFiled: December 29, 2016Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Sonja Koller, Georg Seidemann, Reinhard Mahnkopf, Bernd Waidhas