Abstract: Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Abstract: Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Abstract: A technique for adjusting a power supply for a device is provided. The technique includes detecting a low-power trigger for a device; switching a power supply for the device from a high-power power supply to a low-power power supply; detecting a high-power trigger for a device; and switching a power supply for the device from the low-power power supply to the high-power power supply, wherein the high-power power supply consumes a larger amount of power than the low-power power supply, and wherein the high-power power supply provides a greater amount of noise reducing and a greater tolerance to temperature differences than the low-power power supply.

Abstract: Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Abstract: An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.

Abstract: A system and method directed to determining one or more polls that a user may have missed during a period of inactivity is provided. Initially, a polling system may determine that a user is now active and may determine one or more polls that were created for or assigned to a user, or a group to which the user belongs, during the period of inactivity. The polling system may then surface a notification and/or an input window such that a user may provide polling input. In some instances, a user may have missed multiple polls; the polls presented to the user may be based on recent user activity and/or whether such missed polls are still live, or open.

Abstract: An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.

Abstract: A technique for adjusting a power supply for a device is provided. The technique includes detecting a low-power trigger for a device; switching a power supply for the device from a high-power power supply to a low-power power supply; detecting a high-power trigger for a device; and switching a power supply for the device from the low-power power supply to the high-power power supply, wherein the high-power power supply consumes a larger amount of power than the low-power power supply, and wherein the high-power power supply provides a greater amount of noise reducing and a greater tolerance to temperature differences than the low-power power supply.

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.

Abstract: Described herein is a system that enables a user to filter notable events, representations for which are presented on an interactive timeline associated with a teleconference session or a collaboration environment. The filtering can be implemented based on a type of a notable event and/or based on a specific notable event. The system is also configured to enable a user to search for instances of a type of event and instances of a specific notable event. The system is configured to provide results to the search request that list the teleconference sessions that include the located instances. The user can then select a teleconference session from the results to view an interactive timeline that includes representations of the located instances. Consequently, the system provides a tool that enables a user to efficiently and effectively locate events on an interactive timeline that are desirable (e.g., activity the user wants to view).

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

Abstract: A system and method of displaying a graphical element associated with a poll in a calendar view is provided. Initially, a polling system may determine that a response from a user has not been provided to a poll event. Accordingly, poll information associated with the poll event may be received, where the poll information may indicate a start and end time of a poll. A time slot based on the poll information may be determined which may cause a graphical element for the poll event to be displayed in the calendar view of the user at the determined time slot. In some instances, the graphical element may be provided when a user has missed or otherwise has not provided input into a poll event.

Abstract: A system and method directed to determining one or more polls that a user may have missed during a period of inactivity is provided. Initially, a polling system may determine that a user is now active and may determine one or more polls that were created for or assigned to a user, or a group to which the user belongs, during the period of inactivity. The polling system may then surface a notification and/or an input window such that a user may provide polling input. In some instances, a user may have missed multiple polls; the polls presented to the user may be based on recent user activity and/or whether such missed polls are still live, or open.

Abstract: A system and method for displaying a dashboard interface associated with a plurality of polls is provided. The system and method may receive a user identifier uniquely identifying a user of a system, determine one or more organizational units associated with the user identifier, and cause a dashboard interface associated with a plurality of polls to be rendered at a display, wherein information of a first poll associated with a first organizational unit of the one or more organizational units is provided in a first portion of the dashboard interface and information of a second poll associated with a second organizational unit of the one or more organizational units is provided in a second portion of the dashboard interface.

Abstract: The disclosed system implements techniques to identify activity in which attendees to a communication session likely have a greater interest. Prior to commencement of a communication session or during the communication session, the techniques enable a list of attendees to a communication session to be designated as a group for which detected activity has a priority with respect to being displayed. The designated list of attendees is a subset of a total number of attendees to the communication session. The system monitors streams associated with individual attendees on the list to detect an occurrence of a preset target event. The system configures a portion of a graphical user interface of the communication session to accentuate the stream that includes the occurrence of the preset target event.

Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

Abstract: Described herein is a system that generates and displays a timeline for communication content. The system determines events that occur in association with the communication content (e.g., a video conference, a chat or messaging conversation, etc.). The system adds a representation of an event to the timeline in association with a time at which the event occurs. Moreover, the system enables user interaction with the representation so that the user can view information associated with an event.