Abstract: A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array.

Abstract: A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ?6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to “RAM Flash” memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

Abstract: A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ?6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may be formed with dielectric layers having reduced thickness(es) as compared with conventional flash memory cells, which allows for such low voltage operation. The disclosed memory cells may be compatible with advanced, high density, low energy data computational applications. The disclosed memory cells may replace or reduce the need for RAM (e.g., SRAM or DRAM) in a conventional device, e.g., microcontroller or computer, and are thus referred to “RAM Flash” memory cells. Data retention of RAM Flash memory cells may be increased (e.g., to days, months, or years) by (a) applying a static holding voltage at selected nodes of the cell, and/or (b) periodically refreshing data stored in RAM Flash.

Abstract: Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage VCGR to the control gate.

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-

Abstract: Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage VCGR to the control gate.

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

Abstract: A method is provided for forming a split-gate memory cell having field enhancement regions in the substrate for improved cell performance. The method may include forming a pair of gate structures over a substrate, performing a source implant between the pair of gate structures to form a self-aligned source implant region in the substrate, performing a field enhancement implant process to form field enhancement implant regions, e.g., having an opposite dopant polarity as the source implant, at or adjacent lateral sides of the source implant region, and diffusing the source implant region and field enhancement implant regions to thereby define a source region with field enhanced regions at lateral edges of the source region. The field enhanced implant process may include at least one non-vertical angled implant.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.