Abstract: The write-protected micro memory device of the present invention comprises at least one flash memory that is divided into one or multiple blocks, and the single chip flash memory controller has a write-protected parameter. The write-protect parameter can be set particularly for protecting data of certain block(s) of the flash memory. The memory device is connected to a host, such as a computer or card reader, through an interface circuit, to enable the host to retrieve data or program from the flash memory. The single chip flash memory controller prohibits the host to store or write data into the write-protected block(s) according to the preset write-protect parameter. Accordingly, the present invention do not require altering of the hardware structure or circuit connection of the memory device, but rather merely proposes to set up the write-protect parameter into the single chip flash memory controller to mark any block for substantially protecting the data or program therein.

Abstract: An access and data management method using parallel tracks comprising a plurality of flash memory cells, a plurality of independent USB ports for transferring sets of data from and within said flash memory cells, wherein when a target set of data is a plurality of sectors, then a controller uses a plurality of pages as a single unit to process reading and writing so that a plurality of pages can be read and written into the flash memory cells simultaneously each time. Further the parallel tracks of flash memory cells may be combined with an interleaving method, a mother and child conceptual structure and a copy back method for further enhancing the data processing speed and also extending the life of the flash memory cells.

Abstract: An interleaving management for upgrading the operation speed of flash memory cell is provided. A mother and child concept is applied to process the data of a flash memory cell. The so-called mother and child are two physical features own one logical address at the same time to allow the host to write to a logical address. Thus the controller need not repeat the transferring and erasing actions while writing data to the flash memory cell, accordingly the life of the flash memory cell can be extended and the processing speed can be substantially upgraded.

Abstract: The present invention relates to a management and link structure of a flash memory. The flash memory is divided into several different types of data access blocks, such as general data blocks, spare blocks, link-table block, and new blocks. A simple data link structure is provided, and a management and calculating method for spare blocks saves time to search and write data effectively and prolongs the service life of the flash memory.

Abstract: A single integrated circuit flash memory controller is provided. When the CPU is operating, the operating time of the external ROM and all the flash memory devices are designed or programmed to function in an alternative manner, for example, the flash memory device will not be activated while the external ROM is operating to retrieve the program code. On the contrary, while data is being retrieved from the flash memory device, the CPU will be in a waiting status, in other words, the CPU does not function to retrieve the program code from the external ROM while the data is being retrieved from the flash memory device. Accordingly, this design makes it possible for the single integrated circuit flash memory control to accommodate required connections for connecting with the external ROM as well as all the flash memory device without the need to increasing pin terminals or the size of the integrated circuit package.