Patents by Inventor Sooeun Lee

Sooeun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137750
    Abstract: A method by which a user equipment (UE) operates in a wireless communication system includes obtaining status information of the UE, identifying an execution mode of each function of a plurality of functions being executed by the UE, identifying at least one function whose execution mode is to be changed among the functions being executed by the UE, based on the status information of the UE, and changing the execution mode of the identified at least one function.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 25, 2024
    Inventors: Sangho LEE, Sooeun SONG, Deokhui LEE, Jaehong YI
  • Patent number: 11838398
    Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonju Lee, Jiyoung Kim, Jaehyun Park, Seuk Son, Sooeun Lee, Dongchul Choi
  • Patent number: 11700012
    Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyeongjoon Ko, Junhan Bae, Hanseok Kim, Byeonggyu Park, Jaehyun Park, Hobin Song, Sooeun Lee
  • Publication number: 20230170891
    Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.
    Type: Application
    Filed: October 31, 2022
    Publication date: June 1, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeonju LEE, Jiyoung KIM, Jaehyun PARK, Seuk SON, Sooeun LEE, Dongchul CHOI
  • Publication number: 20220149863
    Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.
    Type: Application
    Filed: May 3, 2021
    Publication date: May 12, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyeongjoon Ko, Junhan Bae, Hanseok Kim, Byeonggyu Park, Jaehyun Park, Hobin Song, Sooeun Lee
  • Patent number: 11221644
    Abstract: A system for transceiving data based on a clock transition time is provided. A transmitting device included in the system includes at least one first transmitting circuit configured to transmit data via a wired channel by changing a clock transition time based on the data, wherein the at least one first transmitting circuit includes a skew controller configured to output a skew clock generated by controlling a duty ratio and a skew of an input clock, and a phase-difference modulator configured to output a transmission signal including information about the data generated by changing a transition time of the skew clock based on the data.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: January 11, 2022
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Sooeun Lee, Byungsub Kim
  • Publication number: 20190354133
    Abstract: A system for transceiving data based on a clock transition time is provided. A transmitting device included in the system includes at least one first transmitting circuit configured to transmit data via a wired channel by changing a clock transition time based on the data, wherein the at least one first transmitting circuit includes a skew controller configured to output a skew clock generated by controlling a duty ratio and a skew of an input clock, and a phase-difference modulator configured to output a transmission signal including information about the data generated by changing a transition time of the skew clock based on the data.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Applicants: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Sooeun Lee, Byungsub Kim