Patents by Inventor Soo-ho Cha
Soo-ho Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127094Abstract: Disclosed herein are a logical qubit execution apparatus and method. The logical qubit execution apparatus may be configured to execute, by a logical execution layer, a quantum circuit including requested logical qubits using a lattice surgery operation, generate, by the logical execution layer, measurement results of the logical qubits by combining measurement results of logical Pauli frames, generate, by a physical execution layer, a physical qubit circuit by converting a logical qubit operation corresponding to the measurement results of the logical qubits into a physical qubit operation, and measure, by the physical execution layer, results of an operation on physical Pauli frames by executing the physical qubit circuit.Type: ApplicationFiled: June 30, 2023Publication date: April 18, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jin-Ho ON, Chei-Yol KIM, Soo-Cheol OH, Sang-Min LEE, Gyu-Il CHA
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Patent number: 10535395Abstract: Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.Type: GrantFiled: May 19, 2017Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo-Ho Cha, Chankyung Kim, Sungchul Park, Kwangchol Choe
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Patent number: 10497427Abstract: Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.Type: GrantFiled: June 1, 2017Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chankyung Kim, Sungchul Park, Soo-Ho Cha, Seongil O, Kwangchol Choe
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Patent number: 10490281Abstract: Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.Type: GrantFiled: June 13, 2017Date of Patent: November 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungchul Park, Chankyung Kim, Soo-Ho Cha
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Patent number: 10446207Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.Type: GrantFiled: January 22, 2019Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rock Oh, Soo-ho Cha
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Patent number: 10332571Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.Type: GrantFiled: April 12, 2018Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo-Ho Cha, Chankyung Kim, Sungchul Park, Hoyoung Song, Kwangchol Choe
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Patent number: 10204670Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.Type: GrantFiled: February 15, 2013Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rock Oh, Soo-ho Cha
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Publication number: 20180233183Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: Soo-Ho Cha, Chankyung Kim, Sungchul Park, Hoyoung Song, Kwangchol Choe
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Patent number: 9972371Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.Type: GrantFiled: May 16, 2017Date of Patent: May 15, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo-Ho Cha, Chankyung Kim, Sungchul Park, Hoyoung Song, Kwangchol Choe
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Publication number: 20180005697Abstract: Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.Type: ApplicationFiled: June 13, 2017Publication date: January 4, 2018Inventors: SUNGCHUL PARK, CHANKYUNG KIM, Soo-Ho CHA
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Publication number: 20170365308Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.Type: ApplicationFiled: May 16, 2017Publication date: December 21, 2017Inventors: SOO-HO CHA, CHANKYUNG KIM, SUNGCHUL PARK, HOYOUNG SONG, KWANGCHOL CHOE
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Publication number: 20170365326Abstract: Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.Type: ApplicationFiled: May 19, 2017Publication date: December 21, 2017Inventors: SOO-HO CHA, CHANKYUNG KIM, SUNGCHUL PARK, KWANGCHOL CHOE
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Publication number: 20170365327Abstract: Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.Type: ApplicationFiled: June 1, 2017Publication date: December 21, 2017Inventors: Chankyung KIM, Sungchul PARK, Soo-Ho CHA, Seongil O, Kwangchol CHOE
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Patent number: 9257166Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.Type: GrantFiled: June 23, 2014Date of Patent: February 9, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chankyung Kim, Dong-Seok Kang, Yunsang Lee, Soo-Ho Cha
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Patent number: 8953368Abstract: A data reading method of a magnetic memory device includes generating read commands, supplying a read current to a selected magnetic memory element in a first direction and in turn in a second direction under different ones of the read commands, respectively, and sensing the magnitude of the read current flowing through the selected magnetic memory element to read data stored at the selected magnetic memory element.Type: GrantFiled: August 15, 2013Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Soo-Ho Cha
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Publication number: 20150036421Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.Type: ApplicationFiled: June 23, 2014Publication date: February 5, 2015Inventors: Chankyung KIM, Dong-Seok KANG, Yunsang LEE, Soo-Ho CHA
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Publication number: 20140140124Abstract: A method of controlling a read operation of a resistive memory device is provided which includes activating at least one of a plurality of word lines in response to a first command; after receiving a second command, sensing data of a memory cell, corresponding to a selected page, from among all memory cells connected with the activated word line through a corresponding bit line sense amplifier; and outputting the sensed data as read data according to a sensing output control signal.Type: ApplicationFiled: November 13, 2013Publication date: May 22, 2014Inventors: Dong-Seok KANG, CHANKYUNG KIM, YUNSANG LEE, Soo-Ho CHA
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Publication number: 20140119107Abstract: A data reading method of a magnetic memory device includes generating read commands, supplying a read current to a selected magnetic memory element in a first direction and in turn in a second direction under different ones of the read commands, respectively, and sensing the magnitude of the read current flowing through the selected magnetic memory element to read data stored at the selected magnetic memory element.Type: ApplicationFiled: August 15, 2013Publication date: May 1, 2014Inventor: SOO-HO CHA
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Publication number: 20140016404Abstract: A magnetic memory device such as a magnetic random access memory (MRAM), and a memory module and a memory system on which the magnetic memory device is mounted are disclosed. The MRAM includes magnetic memory cells each of which varies between at least two states according to a magnetization direction and an interface unit that provides various interface functions. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip that manages an operation of the at least one MRAM chip. The memory system includes the MRAM and a memory controller that communicates with the MRAM, and may communicate an electric-to-optical conversion signal or an optical-to-electric conversion signal by using an optical link that is connected between the MRAM and the memory controller.Type: ApplicationFiled: July 9, 2013Publication date: January 16, 2014Inventors: Chan-kyung Kim, Soo-ho Cha, Dong-seok Kang, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Hye-jin Kim
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Publication number: 20130311717Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.Type: ApplicationFiled: February 15, 2013Publication date: November 21, 2013Applicants: GLOBIT CO., LTD., DIGITAL MEDIA RESEARCH INSTITUTE, INC.Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rok Oh, Soo-ho Cha