Abstract: A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Abstract: An electrocardiogram (ECG) measurement device for a vehicle is provided. The ECG measurement device includes an impedance compensator that corresponds to an electrode in contact with a body of a driver and configured to compensate an impedance of each of electrode signals received from the electrode. An electrode selector sequentially selects the electrode signals in response to receiving the electrode signals from the electrode. A differential amplifier differentially amplifies the electrode signals. In particular, each electrode signal has the compensated impedance. Additionally, a signal quality evaluator evaluates quality of an ECG signal output from the differential amplifier and a compensation controller then adjusts an impedance compensation value of each of the impedance compensators as a result of evaluating the quality of the ECG signal.

Abstract: A method and system for generating a physical identifier in a storage device that includes a plurality of storage regions is provided. The method includes determining a number of reference storage regions for uniquely identifying the storage device; comparing the number of reference storage regions to a threshold; generating auxiliary storage regions for uniquely identifying the storage device, such that a number of the auxiliary storage regions corresponds to a result of the comparison; generating location distribution information of the reference storage regions and auxiliary storage regions; and storing the location distribution information in the storage device.

Abstract: A method and system for generating a physical identifier in a storage device that includes a plurality of storage regions is provided. The method includes determining a number of reference storage regions for uniquely identifying the storage device; comparing the number of reference storage regions to a threshold; generating auxiliary storage regions for uniquely identifying the storage device, such that a number of the auxiliary storage regions corresponds to a result of the comparison; generating location distribution information of the reference storage regions and auxiliary storage regions; and storing the location distribution information in the storage device.

Abstract: A system including a host and a subsystem operatively coupled to the host and having a flash memory is provided. The host reads device information from a memory and provides a predetermined command to the subsystem that changes the multi-source mode to a host mode responsive to the device information. A method for controlling a subsystem and a host is additionally provided. The method includes reading device information from a memory on the subsystem and determining whether the subsystem operates in a multi-source mode responsive to the device information. The method provides a predetermined command to the subsystem so as to change the multi-source mode to a host mode responsive to the determining.

Abstract: Method and apparatus for use with flash memory devices and systems are included among the embodiments. In exemplary systems, a pipelined burst read operation allows the device to support higher data transfer rates than are possible with prior art burst read flash memory devices. Preferably, the flash memory device supports both non-pipelined and pipelined read operations, with the read mode settable from a memory controller. Other embodiments are described and claimed.

Abstract: A system including a host and a subsystem operatively coupled to the host and having a flash memory is provided. The host reads device information from a memory and provides a predetermined command to the subsystem that changes the multi-source mode to a host mode responsive to the device information. A method for controlling a subsystem and a host is additionally provided. The method includes reading device information from a memory on the subsystem and determining whether the subsystem operates in a multi-source mode responsive to the device information. The method provides a predetermined command to the subsystem so as to change the multi-source mode to a host mode responsive to the determining.

Abstract: Method and apparatus for use with flash memory devices and systems are included among the embodiments. In exemplary systems, a pipelined burst read operation allows the device to support higher data transfer rates than are possible with prior art burst read flash memory devices. Preferably, the flash memory device supports both non-pipelined and pipelined read operations, with the read mode settable from a memory controller. Other embodiments are described and claimed.

Abstract: A semiconductor memory device having a plurality of reference cells for detecting states of and verifying written data in plurality of memory cells includes a memory cell array formed of the plurality of memory cells and a reference cell array formed of a plurality of units, each unit formed of the plurality of reference cells, reference cell having a same size as that of each memory cell. A sense amplifier circuit detects a difference between current flowing through a memory cell and a corresponding reference cell. Each unit in the reference cell array is formed of a plurality of the reference cells serially connected between the sense amplifier circuit and a control circuit for controlling the reference cells.

Abstract: A power-on reset circuit reduces power consumption and layout area by utilizing a time delay to deactivate a reset circuit and clamp a reset signal a period of time after a power supply voltage has reached a predetermined level. The reset circuit includes a reset signal generator which maintains the reset signal in an active state until the power supply voltage has reached the predetermined level. The reset signal generator then deactivates the reset signal which causes a delay circuit to begin a time delay after which a delay signal is asserted. The delay signal deactivates a comparator in the reference voltage generator, a voltage detector, and a reset signal generator within the reset circuit, thereby reducing power consumption. The delay signal also activates a clamp circuit which clamps the reset signal to an inactive state.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks having a plurality of memory cells, a plurality of sense amplifiers coupled to the memory cell blocks, and a reference block for generating a reference value and for providing the reference value to the sense amplifiers. Each memory cell block is coupled to at least one of the sense amplifiers. The reference block includes a reference cell for holding a predetermined reference value and a current circuit responsive to a state of the reference cell.

Abstract: Disclosed is a circuit of boosting a voltage which comprises a driver circuit for generating a kick signal for driving word lines via row decoder circuits in an array of flash memory cells during read and program modes of operation. The driver circuit makes both electrodes of a large booster capacitor have the same voltage in order to allow a small charge pump to further pump up the word line voltage during programming.