Abstract: A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO2 layer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins.

Abstract: Vertical transport field effect transistors (VTFET) are disclosed along with methods of making. The VTFET is made with a novel gate last replacement metal gate (RMG) process. The invention allows uniform and high doping levels without adversely affecting the gate region in the process. The distance from the S/D regions and the junctions are the same. Fin caps protect the fins and gate protecting hard mask protect the dummy gate material during the beginning process steps. The invention enables easy connection and increased surface area at the connection points to reduce contact resistance.

Abstract: Embedded BEOL memory devices having a top electrode pillar are provided. In one aspect, a method of forming an embedded memory device includes: depositing a first ILD on a substrate; forming first/second interconnect in the first ILD over logic/memory regions of the substrate; depositing a capping layer onto the first ILD; forming a memory film stack on the capping layer; patterning the memory film stack into a memory device(s) including a bottom electrode, a dielectric element, and a top electrode; patterning the top electrode to form a pillar-shaped top electrode; depositing a conformal encapsulation layer over the capping layer and memory device(s); depositing a second ILD over the conformal encapsulation layer; and forming a first metal line(s) in the second ILD in contact with the first interconnect(s), and a second metal line(s) in the second ILD in contact with the pillar-shaped top electrode. A device is also provided.

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

Abstract: A semiconductor structure is provided utilizing a cost effective method in which the vertical gate channel length is substantially the same for vertical field effect transistors (VFETs) that are present in a dense device region and an isolated device region. The VFETs have improved uniformity, device functionality and better yield. No additional lithographic process is used in making such a semiconductor structure.

Abstract: A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first area and contacts a surface of one of the second electrically conductive structures that contacts a surface of an underlying first electrically conductive structure, and the other of the sacrificial conductive pads has a second area, different from the first area, and contacts a surface of another of the second electrically conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and to convert a dielectric switching material of the patterned material stack into a conductive filament. After plasma treatment, the pair of sacrificial conductive pads is removed.

Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

Abstract: A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Abstract: Embedded BEOL memory devices having a top electrode pillar are provided. In one aspect, a method of forming an embedded memory device includes: depositing a first ILD on a substrate; forming first/second interconnect in the first ILD over logic/memory regions of the substrate; depositing a capping layer onto the first ILD; forming a memory film stack on the capping layer; patterning the memory film stack into a memory device(s) including a bottom electrode, a dielectric element, and a top electrode; patterning the top electrode to form a pillar-shaped top electrode; depositing a conformal encapsulation layer over the capping layer and memory device(s); depositing a second ILD over the conformal encapsulation layer; and forming a first metal line(s) in the second ILD in contact with the first interconnect(s), and a second metal line(s) in the second ILD in contact with the pillar-shaped top electrode. A device is also provided.

Abstract: Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

Abstract: A method of forming a semiconductor structure includes forming a metal liner above and in direct contact with a bottom source/drain region, a fin spacer on sidewalls of a fin extending upward from a substrate and a hard mask positioned on top of the fin, the bottom source/drain region includes an epitaxially grown material in direct contact with a bottom portion of the fin not covered by the fin spacer, forming an organic planarization layer directly above the metal liner, simultaneously etching the organic planarization layer and the metal liner until all portions of the metal liner perpendicular to the substrate have been removed and only portions of the metal liner parallel to the substrate remain in contact with the bottom source/drain region, and annealing the semiconductor structure to form a metal silicide layer from the portions of the metal liner in contact with the bottom source/drain region.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.

Abstract: A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.

Abstract: A method for making a semiconductor includes patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor, and etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.

Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.

Abstract: A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first area and contacts a surface of one of the second electrically conductive structures that contacts a surface of an underlying first electrically conductive structure, and the other of the sacrificial conductive pads has a second area, different from the first area, and contacts a surface of another of the second electrically conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and to convert a dielectric switching material of the patterned material stack into a conductive filament. After plasma treatment, the pair of sacrificial conductive pads is removed.

Abstract: A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.

Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

Abstract: Embodiments of the invention are directed to an integrated circuit structure that includes a resistive switching device (RSD). The RSD includes a bottom electrode, an insulator region, and a top electrode. The insulator region includes a filament region and is communicatively coupled to the bottom electrode. The top electrode is communicatively coupled to the insulator region. The filament region includes an apex region having a first apex region sidewall and a second apex region sidewall that intersects the first apex region sidewall at an angle that is less than about 90 degrees.

Abstract: Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets.