Abstract: There is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the column address buffering circuit generates specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto. Such an arrangement synchronizes the generation time of the specific internal address signals with those of other internal address signals by positioning a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled.

Abstract: There is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the column address buffering circuit generates specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto. Such an arrangement synchronizes the generation time of the specific internal address signals with those of other internal address signals by positioning a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled.

Abstract: In a memory module having a plurality of memory chips and a plurality of data switchers on one board, wherein each data switcher is selectively turned on or off in response to a switcher control signal to connect corresponding memory chip with a common data bus line, an apparatus for generating the switcher control signal includes: a plurality of shift counting units for shift counting a write command signal in response to an internal clock signal and a reset signal, to generate a plurality of shift counting signals; a switcher enable control signal generator for receiving the shift counting signals to generate a switcher enable control signal for enabling the switcher control signal during a predetermined time corresponding to a burst length; a pull down driver for pulling down the switcher control enable signal to generate a pull-down signal; and an output unit for outputting the switcher control signal in response to the pull-down signal.

Abstract: A semiconductor memory device includes: a global I/O line pair having a global I/O line and a complementary global I/O line; a data I/O buffer unit, coupled to the global I/O line pair; a plurality of banks, coupled to the global I/O line pair, for storing data, said banks including: a first bank coupled to the global I/O line pair; and a second bank coupled to the global I/O line pair, wherein the second bank is located closer to the data I/O buffer unit than the first bank is; a control signal generating unit for generating a control signal, said control signal has a first level and a second level in a read operation and a write operation, respectively; a first precharge unit located closely to said first bank, said first precharge unit sensing a level transition of the global I/O line pair and precharging the global I/O line pair in response to the control signal of the second level in a write operation; and a second precharge unit located closely to said second bank, said second precharge unit sensing a l

Abstract: A column redundancy circuit prevents a time delay in the normal and repair operations without using an additional input/output line and input/output sense-amp. In the column redundancy circuit, since a normal Y-decoder does not receive an output signal of a fuse box when a column line is enabled, a column enable operation speed increases, and a complete repair operation having no error is achieved without using an additional circuit in a repair operation.