Abstract: A serial communication method for a layered communication architecture includes a first layer, a second layer that is higher than the first layer, and a third layer that is higher than the second layer. The serial communication method includes transferring a first signal to the second layer based on a signal received through a communication line, the transferring performed by the first layer. The serial communication method further includes informing the third layer of reception of the first signal, the informing performed by the second layer; responding to the second layer based on whether there is a task to be performed, the responding performed by the third layer; transferring a second signal to the first layer based on a response from the third layer the transferring performed by the second layer; and entering a power saving state according to the second signal, the entering performed by the first layer.

Abstract: A serial communication method for a layered communication architecture includes a first layer, a second layer that is higher than the first layer, and a third layer that is higher than the second layer. The serial communication method includes transferring a first signal to the second layer based on a signal received through a communication line, the transferring performed by the first layer. The serial communication method further includes informing the third layer of reception of the first signal, the informing performed by the second layer; responding to the second layer based on whether there is a task to be performed, the responding performed by the third layer; transferring a second signal to the first layer based on a response from the third layer the transferring performed by the second layer; and entering a power saving state according to the second signal, the entering performed by the first layer.

Abstract: A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that is connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

Abstract: A voltage scaling device of a semiconductor memory device, the voltage scaling device including: a delay tester for determining the number of delay cells of a delay locked loop (DLL) required to cumulatively delay a clock signal having a constant frequency, and which is input to the DLL, by one clock period; a temperature sensor for measuring the temperature of the semiconductor memory device; and a voltage regulator for regulating a supply voltage of a voltage source which provides a chip voltage to the semiconductor memory device in response to the temperature measured by the temperature sensor and a locking value corresponding to the number of delay cells calculated by the delay tester.

Abstract: A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that i s connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

Abstract: A NAND flash memory device comprises a NAND flash memory comprising a first pad and a plurality of second pads. The first pad comprises a first receiver configured to receive a first signal. The second pads comprise a plurality of respective second receivers configured to receive a plurality of respective second signals. The second receivers are selectively powered, i.e., turned on or off, according to a logic level of the first signal.

Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Abstract: A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

Abstract: A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

Abstract: The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.