Patents by Inventor Sophie Verrun

Sophie Verrun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Assembly of a wire element with a microelectronic chip with a groove comprising at least one bump securing the wire element
    Patent number: 8723312
    Abstract: The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: May 13, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Dominique Vicard, Sophie Verrun
  • Assembly of a microelectronic chip having a groove with a wire element in the form of a strand, and method for assembly
    Patent number: 8611101
    Abstract: Assembly of at least one microelectronic chip with a wire element, the chip comprising a groove for embedment of the wire element. The wire element is a strand with a longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires covered with insulator. The chip comprises at least one electrically conducting bump in the groove, this bump being in electric contact with a stripped area of a single one of the electrically conducting wires of the strand.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: December 17, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Sophie Verrun, Dominique Vicard
  • 3D integration of vertical components in reconstituted substrates
    Patent number: 8039306
    Abstract: A reconstituted electronic device including: a first face and a second face; a plurality of individual chips placed perpendicular to the faces, each individual chip carrying, on one of its surfaces, at least one component, tracks, and a connection mechanism that are flush with one or other of the faces of the reconstituted electronic device; and an encapsulant that encapsulates the individual chips.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: October 18, 2011
    Assignee: Commissariat A l'Energie Atomique
    Inventors: François Baleras, Jean-Charles Souriau, Gilles Poupon, Sophie Verrun
  • ASSEMBLY OF A MICROELECTRONIC CHIP HAVING A GROOVE WITH A WIRE ELEMENT IN THE FORM OF A STRAND, AND METHOD FOR ASSEMBLY
    Publication number: 20110198735
    Abstract: Assembly of at least one microelectronic chip with a wire element, the chip comprising a groove for embedment of the wire element. The wire element is a strand with a longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires covered with insulator. The chip comprises at least one electrically conducting bump in the groove, this bump being in electric contact with a stripped area of a single one of the electrically conducting wires of the strand.
    Type: Application
    Filed: October 21, 2009
    Publication date: August 18, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean Brun, Sophie Verrun, Dominique Vicard
  • ASSEMBLY OF A WIRE ELEMENT WITH A MICROELECTRONIC CHIP WITH A GROOVE COMPRISING AT LEAST ONE BUMP SECURING THE WIRE ELEMENT
    Publication number: 20110001237
    Abstract: The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.
    Type: Application
    Filed: October 21, 2008
    Publication date: January 6, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean Brun, Dominique Vicard, Sophie Verrun
  • 3D INTEGRATION OF VERTICAL COMPONENTS IN RECONSTITUTED SUBSTRATES
    Publication number: 20100181679
    Abstract: A reconstituted electronic device including: a first face and a second face; a plurality of individual chips placed perpendicular to the faces, each individual chip carrying, on one of its surfaces, at least one component, tracks, and a connection mechanism that are flush with one or other of the faces of the reconstituted electronic device; and an encapsulant that encapsulates the individual chips.
    Type: Application
    Filed: June 5, 2008
    Publication date: July 22, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Francois Baleras, Jean-Charles Souriau, Gilles Poupon, Sophie Verrun