Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operation, a portion of the data manipulation instruction indicating an expansion operation from a number of predetermined types of data manipulation operations. The method includes generating one or more expansion objects responsive to the indication of an expansion operation, said expansion objects being for use in extending an input data object. The input data objects are manipulated according to control information expansion objects programmed to produce a set of expanded output data objects.

Abstract: An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a single operation or two independent operations. The instruction includes designated bits at predetermined bit locations which identify whether the instruction is a long instruction or a dual operation instruction.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A method and system for conditionally carrying out an operation defined in a computer instruction wherein a computer instruction is implemented on so-called packed operands; that is, operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in dependence on stored condition values which determine for each lane whether or not the operation is to be executed on objects in that lane.

Abstract: A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the method comprising receiving and decoding instruction fields to determine at least one source store, a plurality of destination stores and at least one control store, said source and destination stores being capable of holding one or a plurality of objects, each object defining a SIMD lane. Conditional execution of the operation on a per SIMD lane basis is controlled using a plurality of pre-set indicators of the at least one control store designated in the instruction, wherein each said pre-set indicator i controls a predetermined number of result lanes p, where p takes a value greater than or equal to two. A predetermined number of result objects are sent to the destination stores such that the predetermined number of result objects are held by a combination of different ones of the plurality of destination stores.

Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.

Abstract: A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the method comprising receiving and decoding instruction fields to determine at least one source store, a plurality of destination stores and at least one control store, said source and destination stores being capable of holding one or a plurality of objects, each object defining a SIMD lane. Conditional execution of the operation on a per SIMD lane basis is controlled using a plurality of pre-set indicators of the at least one control store designated in the instruction, wherein each said pre-set indicator i controls a predetermined number of result lanes p, where p takes a value greater than or equal to two. A predetermined number of result objects are sent to the destination stores such that the predetermined number of result objects are held by a combination of different ones of the plurality of destination stores.

Abstract: A computer system is disclosed capable of conditionally carrying out an operation defined in a computer instruction. The computer instruction is implemented on so-called packed operands, that is operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in dependence on stored condition values which determine for each lane whether or not the operation is to be executed on objects in that lane. An execution unit for a computer system, a computer system and a method of executing instructions are defined.

Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: A method for setting indicators in a control store of a computer system for conditionally performing operations, comprises providing a control store setting instruction defining an execution condition and specifying a control store to be set according to the condition, specifying in the instruction an operand lane size over which a setting operation is to be performed, the operand lane size specified being selected from a plurality of predetermined operand lane sizes, performing the setting operation defined in the setting instruction on a per operand lane basis over a plurality of operand lanes, writing the result of the setting operation to the control store specified in the instruction to set a plurality of indicators on a lane by lane basis, wherein one or a predetermined plurality of indicators is set for each operand lane in dependence on the size of the operand lane defined in the instruction. An instruction for performing the preferred method is also disclosed.

Abstract: A method is provided of processing data representing pixel color having a luminance component and color difference components. The data is divided into first and second data portions, the first data portion comprising the luminance components and the second data portion comprising the color difference components. First and second instructions from a combined instruction word, and the first and second date portions are processed in parallel using first and second parallel processors within a processor architecture, the first and second parallel processors operating according to the first and second instructions, respectively. The processed first and second data portions are combined to provide processed pixel color data. This method uses parallel processor sections to process the luminance and color difference components. The parallel processor sections can then use instructions suited to the type of data being processed, providing an efficient method of processing the graphics data.

Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, said condition bits being adapted for indicating respective conditions. The front end is adapted for resolving conditional branch instructions by accessing said array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit. In another embodiment, the condition bits are combined with predicated execution of instructions, with the instruction's predicates being evaluated at the processing pipeline's back end.

Abstract: A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operation, a portion of the data manipulation instruction indicating an expansion operation from a number of predetermined types of data manipulation operations. The method includes generating one or more expansion objects responsive to the indication of an expansion operation, said expansion objects being for use in extending an input data object. The input data objects and said expansion objects are manipulated according to control information programmed to produce a set of expanded output data objects.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache. The present invention improves the of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code.