Patents by Inventor Sorabh Sachdeva

Sorabh Sachdeva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit design synthesis using slack diagrams
    Patent number: 9330216
    Abstract: An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mohit Parnami, Sorabh Sachdeva
  • IC DESIGN SYNTHESIS USING SLACK DIAGRAMS
    Publication number: 20150379175
    Abstract: An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mohit Parnami, Sorabh Sachdeva