Abstract: A method for determining a reifetch address of a branch instruction in a set of instructions involves decoding the set of instructions, forwarding the set of instructions along with a value of a branch counter, updating the branch counter based on the set of instructions, and predicting a result of executing the branch instruction in the set of instructions. If mispredicted, a source address of the branch instruction is calculated. The calculating involves shifting the value of the branch counter dependent on a shift value to generate a shifted value of the branch counter, and adding a working copy of the program counter or next program counter and the shifted value of the branch counter to generate the source address which is in turn used to determine the reifetch address.

Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.

Abstract: A method and apparatus for processing instructions involves an instruction fetch unit arranged to receive a plurality of instructions. The instruction fetch unit includes a bypass buffer arranged to receive at least a portion of a plurality of instructions, and an output multiplexer arranged to receive the at least a portion of the plurality of instructions where the output multiplexer is arranged to output an instruction selected from one of an output of the bypass buffer and the at least a portion of the plurality of instructions.

Abstract: A method and apparatus for avoiding strand starvation is provided. The method and apparatus selectively switches from a first strand to a second strand dependent on a state of a computer system. The selectively switching is dependent on whether the second strand is alive and whether a value of a counter has reached a particular count.

Abstract: A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.

Abstract: In an embodiment, the present invention describes a method and apparatus for detecting RAW condition earlier in an instruction pipeline. The store instructions are stored in a special store bypass buffer (SBB) within an instruction decode unit (IDU). The IDU compares the instruction fields that are used for address generation of all ‘load’ instructions against ‘store’ instructions within a group of fetched instructions and ‘store’ instructions previously stored in the SBB. If a match of instruction fields is found, the IDU ‘speculates’ that the load instruction has dependency on the ‘store’ instruction. A data cache unit (DCU) validates the dependency of the load instruction ‘speculated’ by the IDU. If a false dependency is ‘speculated’ by the IDU, the DCU forces a re-fetch of the load instruction.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.

Abstract: An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

Abstract: An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

Abstract: An apparatus in a computer, called a pending access queue, for providing data for register load instructions after a cache miss. After a cache miss, when data is available for a register load instruction, the data is first directed to the pending access queue and is provided to an execution pipeline directly from the pending access queue, without requiring the data to be entered in the cache. Entries in the pending access queue include destination register identification, enabling injection of the data into the pipeline during intermediate pipeline phases. The pending access queue provides results to the requesting unit in any order needed, supporting out-of-order cache returns, and provides for arbitration when multiple sources have data ready to be processed. Each separate request to a single line is provided a separate entry, and each entry is provided with its appropriate part of the line as soon as the line is available, thereby rapidly providing data for multiple misses to a single line.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

Abstract: A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.

Abstract: A computer memory cache system that includes hardware (called a conflict cache) for short term tolerance and reduction of cache misses and including counters to enable software to detect and remove longer term cache misses through dynamic page remapping. In an example embodiment, when a conflict miss occurs for a low associativity cache, the address of the displaced item is saved in a content addressable memory and the corresponding data is saved in a data RAM. The operating system logically partitions the low associativity cache into bins, where the address range for a bin is a page or multiple pages. Every logical bin in the low associativity cache has a corresponding counter in the conflict cache. Each bin counter counts the number of conflict misses for the corresponding bin. When a bin counter exceeds a predetermined value, the operating system remaps a corresponding page.

Abstract: A simplified semaphore method and apparatus for simultaneous execution of multiple semaphore instructions and for enforcement of necessary ordering. A central processing unit having an instruction pipeline is coupled with a data cache arrangement including a semaphore buffer, a data cache, and the semaphore execution unit. An initial semaphore instruction having one or more operands and a semaphore address are transmitted from the instruction pipeline to the semaphore buffer, which in turn are transmitted from the semaphore buffer to the semaphore execution unit. The semaphore address of the initial semaphore instruction is transmitted from the instruction pipeline to the data cache to retrieve initial semaphore data stored within the data cache at a location in a data line of the data cache as identified by the semaphore address.

Abstract: An apparatus including a cache subsystem arrangement for efficient management of input/output operations and of memory shared by processors in a multiprocessor system. The apparatus includes a central processing unit, an input/output device such as a network device or a display device for example, and the cache arrangement, which includes a coalescing buffer coupled with the data processing unit for receiving non-cacheable data from the processing unit. The non-cacheable data is combined in the coalescing buffer into non-cacheable data blocks. A system bus is coupled with the buffer and the input/output device for storing the non-cacheable data blocks to the input/output device. By combining the non-cacheable data before storage to the input/output device, the coalescing buffer provides higher performance in the multiprocessor system, since fewer bus transactions are issued for serial store operations and more stores can complete in a given amount of time than if they were issued singly on the bus.

Abstract: A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least one buffer queue for storing the address of the cache data line and the status of the cache data line, which facilitate keeping track of the data requests and handling them efficiently. In response to a snoop request, a snoop address is compared to the address stored in the buffer queue so as to provide a positive comparison result if the snoop address matches the address stored in the buffer queue, thereby indicating a snoop hit condition. The buffer queue of the cache arrangement further has a snoop hit bit for storing a record of the positive comparison result that indicates the snoop hit condition.

Abstract: A processor emulation system for testing processor operation. First and second identical microprocessors are used together with a target system which includes the main memory. One microprocessor performs an in-system emulation (ISE) function by operating in lock step with the second processor which functions as the master processor. A mode control signal is used to switch the microprocessors between a normal operating mode and an ISE mode. Normal microprocessor signals are outputted on predetermined terminals for the processor in the normal operating mode and the parallel contents of the processor program counter are outputted on the same predetermined terminals when the microprocessor is in the ISE mode. The master processor provides output signals to the target system, with the ISE processor and the master processor both receiving signals from the target system. Operation of the master processor can be ascertained by monitoring the program counter output of the ISE processor.