Patents by Inventor Soseki ANIYA

Soseki ANIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating-point error detection and correction
    Patent number: 9104515
    Abstract: An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first operand to a first comparison register. The method may also include copying a second exponent of the second operand to a second comparison register. The method may further include comparing the first exponent in the first comparison register to the second exponent in the second comparison register. Based on the comparison, a determination may be made whether the instruction includes a potential floating-point error when executing the instruction using the first operand and the second operand formatted according to a first precision.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 11, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Mitsuru Tomono, Hiroaki Yoshida, Soseki Aniya
  • FLOATING-POINT ERROR DETECTION AND CORRECTION
    Publication number: 20140172936
    Abstract: An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first operand to a first comparison register. The method may also include copying a second exponent of the second operand to a second comparison register. The method may further include comparing the first exponent in the first comparison register to the second exponent in the second comparison register. Based on the comparison, a determination may be made whether the instruction includes a potential floating-point error when executing the instruction using the first operand and the second operand formatted according to a first precision.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Mitsuru TOMONO, Hiroaki YOSHIDA, Soseki ANIYA