Patents by Inventor Souichi Okita

Souichi Okita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8766331
    Abstract: In a semiconductor module according to certain aspects the invention, a U-terminal and an M-terminal overlap each other in a manner to reduce inductance and to further to reduce the size of snubber capacitor. In certain aspects of the invention, a P-terminal, M-terminal, N-terminal, and U-terminal are arranged such that the U-terminal, through which currents flow in and out, is arranged farthest away from control electrodes to reduce the noises superposed to control electrodes, and the P-terminal, M-terminal, N-terminal, and U-terminal are aligned to facilitate attaching external connection bars thereto. A power semiconductor module according to aspects of the invention can facilitate reducing the wiring inductance inside and outside the module, reducing the electromagnetic noises introduced into the control terminals, and attaching the external wirings to the terminals thereof simply and easily.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 1, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Souichi Okita
  • Patent number: 8405205
    Abstract: A power semiconductor module includes a plurality of sets of semiconductor switching elements, a molded resin casing containing the semiconductor switching elements, screw holders for receiving mounting screws formed at bottom regions of four corners of the molded resin casing, first terminal blocks having main circuit terminals, and arranged on a central region of a top surface of the molded resin casing, and second terminal blocks having control terminals arranged at a side edge of the molded resin casing apart. Insulating separation walls having a configuration of a rib erect from a surface of the second terminal blocks, and are interposed between groups of the control terminals corresponding to the sets of semiconductor switching elements, and between the screw holder including the mounting screw therein on the molded resin casing and the control terminal at a high voltage side adjacent to the screw holder.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 26, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kiyoshi Takahashi, Souichi Okita
  • Publication number: 20120119256
    Abstract: In a semiconductor module according to certain aspects the invention, a U-terminal and an M-terminal overlap each other in a manner to reduce inductance and to further to reduce the size of snubber capacitor. In certain aspects of the invention, a P-terminal, M-terminal, N-terminal, and U-terminal are arranged such that the U-terminal, through which currents flow in and out, is arranged farthest away from control electrodes to reduce the noises superposed to control electrodes, and the P-terminal, M-terminal, N-terminal, and U-terminal are aligned to facilitate attaching external connection bars thereto. A power semiconductor module according to aspects of the invention can facilitate reducing the wiring inductance inside and outside the module, reducing the electromagnetic noises introduced into the control terminals, and attaching the external wirings to the terminals thereof simply and easily.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 17, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Souichi OKITA
  • Publication number: 20120001227
    Abstract: A power semiconductor module includes a plurality of sets of semiconductor switching elements, a molded resin casing containing the semiconductor switching elements, screw holders for receiving mounting screws formed at bottom regions of four corners of the molded resin casing, first terminal blocks having main circuit terminals, and arranged on a central region of a top surface of the molded resin casing, and second terminal blocks having control terminals arranged at a side edge of the molded resin casing apart. Insulating separation walls having a configuration of a rib erect from a surface of the second terminal blocks, and are interposed between groups of the control terminals corresponding to the sets of semiconductor switching elements, and between the screw holder including the mounting screw therein on the molded resin casing and the control terminal at a high voltage side adjacent to the screw holder.
    Type: Application
    Filed: June 14, 2011
    Publication date: January 5, 2012
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Kiyoshi Takahashi, Souichi Okita
  • Patent number: 7187074
    Abstract: A semiconductor or electronic device, such as a power module uses at least one spring terminal as a control terminal. The spring terminal is led outside a case through a coil-accommodating member, which can be a frame or removable cover. With this arrangement, the spring terminal can be arranged at an arbitrary position inside the case. The spring terminal can be joined by soldering or bonding to the electrode of an in-case substrate while being held by the frame or cover. The in-case substrate can be accessed for solder joining through at least one aperture formed in the frame.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 6, 2007
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Taku Uchiyama, Souichi Okita
  • Publication number: 20050280490
    Abstract: A semiconductor or electronic device, such as a power module uses at least one spring terminal as a control terminal. The spring terminal is led outside a case through a coil-accommodating member, which can be a frame or removable cover. With this arrangement, the spring terminal can be arranged at an arbitrary position inside the case. The spring terminal can be joined by soldering or bonding to the electrode of an in-case substrate while being held by the frame or cover. The in-case substrate can be accessed for solder joining through at least one aperture formed in the frame.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 22, 2005
    Applicant: Fuji Electric Device Technology Co., Ltd.
    Inventors: Taku Uchiyama, Souichi Okita
  • Patent number: 6844621
    Abstract: A semiconductor device has an insulating substrate with conductor patterns bonded to and formed on both the top and bottom surfaces of a ceramic substrate. Soldering is provided between the conductor pattern on the top surface side and a heat developing chip component such as a power semiconductor element is mounted thereon. Between the conductor pattern on the bottom surface side and a heat dissipating metal base plate, each of four corners of the ceramic substrate is chamfered to form a chamfered section with a chamfered dimension of 2 to 10 mm. Alternatively, slits can be formed at the four corners on the bottom surface side. Moreover, the thickness of the conductor patterns can be controlled in relation to the ceramic substrate. These configurations relax the stress concentration created in the soldered section due to a thermal cycle.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: January 18, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Morozumi, Yoshitaka Nishimura, Souichi Okita
  • Publication number: 20040102023
    Abstract: A semiconductor device has an insulating substrate with conductor patterns bonded to and formed on both the top and bottom surfaces of a ceramic substrate. Soldering is provided between the conductor pattern on the top surface side and a heat developing chip component such as a power semiconductor element is mounted thereon. Between the conductor pattern on the bottom surface side and a heat dissipating metal base plate, each of four corners of the ceramic substrate is chamfered to form a chamfered section with a chamfered dimension of 2 to 10 mm. Alternatively, slits can be formed at the four corners on the bottom surface side. Moreover, the thickness of the conductor patterns can be controlled in relation to the ceramic substrate. These configurations relax the stress concentration created in the soldered section due to a thermal cycle.
    Type: Application
    Filed: August 13, 2003
    Publication date: May 27, 2004
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Akira Morozumi, Yoshitaka Nishimura, Souichi Okita
  • Patent number: 6262474
    Abstract: A semiconductor device is formed of a casing, a substrate situated in the casing, at least one semiconductor chip fixed on the substrate, and at least one lead-out terminal for connecting the semiconductor chip to outside. The lead-out terminal includes a soldered portion soldered to the substrate, and a fixed portion fixed to the casing. A stress relaxing device or cutout is formed between the soldered portion and the fixed portion of the lead-out terminal to relieve stress along three axial directions orthogonal to each other. Thus, the crack formation is prevented in the soldered portion of the lead-out terminal while the resistance and impedance of the lead-out terminal are maintained at low values.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: July 17, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Kobayashi, Souichi Okita, Rikihiro Maruyama