Abstract: Test vectors for a circuit containing both logic gates and memory blocks are evaluated by applying candidate test vectors to good and faulty versions of the circuit in a computer simulation. The functions of the gates and interconnections in the circuit are stored in memory and the operation of the good and faulty circuits is simulated concurrently. During the simulation, a memory record is created for storing the state of a circuit element in a faulty circuit if the fault is visible at the element. Such records are removed when no longer needed, which speeds up the simulation. A multiprocessor in a pipeline configuration is disclosed for performing the simulation. A first branch in the pipeline simulates the logic gates in the circuit; a second branch simulates the memory blocks.