Abstract: An apparatus and method of application virtualization is disclosed. In one embodiment, a method includes automatically generating a virtual execution environment of an application-enabled drive, installing the virtual execution environment in user mode on a host system when the application-drive is electrically coupled to the host system, detecting any changes made to an operating system of the host system, and moving the virtual execution environment from the host system to the application-enabled drive when the application-enabled drive is electrically decoupled from the host system. A plurality of systems file modification of a host system may be detected due to an application installation. The plurality of systems file modification of the host system may be made by the application installation in the virtual execution environment. The plurality of systems file modification of the host system may be deleted when the application-enabled drive is electrically decoupled from the host system.

Abstract: Apparatuses and methods of an expandable portable solid-state device are disclosed. In one embodiment, a solid-state device includes an expansion canister to enable coupling of a flash memory of the solid-state device to an external storage memory, and an executable-in-place module of the solid state device coupled to the flash memory to process a swap data to minimize a number of write operations in the flash memory. The executable-in-place module may include a secondary flash memory coupled to a dynamic random access memory. The dynamic random access memory may store at least as much data as the secondary flash memory. A logic circuit coupled to the secondary flash memory and the dynamic random access memory may copy data from the secondary flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device.

Abstract: Apparatuses and methods of an executable-in-place solid-state device are disclosed. In one embodiment, a solid-state device includes a flash memory coupled to a dynamic random access memory, the dynamic random access memory to store at least as much data as the flash memory; and a logic circuit coupled to the flash memory and the dynamic access memory to copy data from the flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device. The logic circuit is to minimize writes to the flash memory by using the dynamic access memory as a working memory during operation of the data processing system, and/or to block at least some sectors of at least one of the flash memory and the dynamic random access memory when the data processing system uses the working memory to conserve power usage of the solid-state device.

Abstract: An apparatus for security applications, e.g., encryption. The apparatus has an interface (e.g., MAC) coupled to a fiber channel. The interface is adapted to receive a frame from the fiber channel. The apparatus also has a classifier coupled to the interface, which is adapted to determine an information type associated with the frame. The type is selected from at least an initiator, data, or terminator. The classifier is adapted to determine header information associated with the frame. A content addressable memory is coupled to the classifier.

Abstract: A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread.

Abstract: One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

Abstract: A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory of a next guest instruction to be emulated, and an indication of a particular native instruction are stored. After an interrupt handler is executed, emulation is resumed by executing native instructions beginning with the particular native instruction. In response to execution of a native instruction of a first type before execution of a native instruction of a second type, the current guest instruction is fetched from memory.

Abstract: A processor and method of executing a program within a processor are provided. According to the method, a plurality of program instructions comprising a program and a set of auxiliary instructions are stored. An instruction stream including selected ones of the plurality of program instructions is supplied to the processor. In response to the processor processing a program instruction within the instruction stream that has an associated auxiliary instruction within the set of auxiliary instructions, the associated auxiliary instruction is automatically inserted within the instruction stream and the associated auxiliary instruction is executed within the processor.

Abstract: A series of guest instructions including at least one guest branch instruction and other guest instructions are stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each other guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt of the other guest instructions. Each entry includes an indication of a location in memory of at least one semantic routine and a condition field indicating conditions that may be set or reset by the associated guest instruction. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines.

Abstract: A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in memory. The series includes a guest memory access instruction that indicates a guest logical address in guest address space. For each guest instruction in the series, a semantic routine of native instructions from the native instruction set is stored in memory. The semantic routines, which utilize native addresses in native address space, can be executed in order to emulate the guest instructions. In response to receipt of the guest memory access instruction for emulation, the guest logical address is translated into a guest real address, which is thereafter translated into a native physical address. A semantic routine that emulates the guest memory access instruction is then executed utilizing the native physical address.

Abstract: A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.

Abstract: A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

Abstract: In a method and system for storing information within a set of a cache memory, the set has multiple locations. The information is stored at a selected one of the locations. The selected location satisfies one of the following conditions (a), (b) and (c): (a) the selected location is invalid; (b) each of the locations is valid, and the selected location is unmodified; (c) each of the locations is valid and modified, and the selected location is least recently used among the locations.

Abstract: A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off.

Abstract: A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register.

Abstract: A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.

Abstract: A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.

Abstract: A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

Abstract: While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0<M<N.

Abstract: A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of guest instructions including at least one unconditional indirect guest branch instruction is stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt. The entry includes an indication of a location in memory of at least one semantic routine. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines.